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RF Design

Agere Systems

Design Challenge
	Adopt a new verification environment to enable hardware/software co-verification
	Speed development time for 6-million-gate Link Layer Processor
Cadence Solution
	Demonstrated the power of the Cadence Palladium® accelerator/ emulator by bringing up a new verification environment in only two weeks
	Success of initial project convinced Agere to choose the Incisive Palladium II system for future designs
Read Full story»

Agilent Technologies Chris Silsby Agilent Technologies Chris Silsby from Agilent Technologies talks about how the Virtuoso accelerated layout technologies help Agilent complete a variety of experiments in hours instead of weeks, and complete the project on schedule.

austriamicrosystems Douglas Pattullo austriamicrosystems Douglas Pattullo talks about how the robust and stable technologies from the Virtuoso custom design platform help austriamicrosystems build design kits that facilitate fast, productive design to market.

Digeo Toby Farrand Digeo Toby Farrand, Chief Technical Officer of Digeo talks about how Digeo and Cadence Engineerings Services collaborate to achieve first silicon success on X-Stream project.

Epoch Microelectronics

Design Challenge
	Larger chips but shorter design cycles
	Integrating an entire transceiver supporting multiple standards onto a single SoC
Cadence Solution
	Integrated full-chip RF design and simulation methodology
	Mixed-signal verification
Read Full story »

Intrinsity Tom Rudwick Intrinsity Tom Rudwick of Intrinsity talks about how the Virtuoso accelerated layout technologies, with its easy-to-use shape-based router, help Intrinsity to meet electromigration constraints and design to volume.

NemeriX

Design Challenge
	Achieve the lowest possible power consumption for new GPS chipset
	Complete back-end process for complex design in two months
Cadence Solution
	Deployed the Cadence Encounter® digital IC design platform low-power flow using Virage ultra-high-density (UHD) libraries to address both front- and back-end design challenges
	Trained NemeriX engineering team on best practices for future designs
Read Full story »

NemeriX Vincent Mouret NemeriX Vincent Mouret, CEO of NemeriX talks about how NemeriX and Cadence team up to produce industry leading GPS Chipset.

Realtek

Design Challenge
	Shorter design cycles
	Simulation of larger, more complex mixed-signal designs
Cadence Solution
	Large-capacity design and verification based on known database structures
	Mixed-signal verification using FastSPICE technology
Read Full story »

Sipex Steve Stern Sipex Steve Stern from Sipex talks about how the Virtuoso custom design platform and Cadence Engineering Services provided technologies and methodologies that reduced design cycle time from months to weeks and increased employee retention.

Teradyne

Design Challenge
	Complex analog and mixed-signal SoC simulations
	Wide variety of applications and test priorities
Cadence Solution
	Token-based licensing model for flexible simulation solutions over a wide range of design verification requirements
	Increased speed to market from a single testbench configuration directly integrated to the design process
Read Full story »

Virage Logic Ken Rousseau Virage Logic Ken Rousseau, VP Software Development of Virage Logic talks about how Virage Logic delivers memory compiler using high-performance, industry-standard Virtuoso custom IC layout.

Zeevo

Edwin Li

Zeevo
Edwin Li, Ph.D. from Zeevo talks about how the Virtuoso custom design platforms speeds the design of highly integrated Bluetooth SoC RF modules by enabling simulation of designs at real-time 2.4-gigahertz speed through the Virtuoso AMS Designer Simulator.