Home > Tools > RF Design > Customer Success

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Company Location *

Comments: *

RF Design 

Agere Systems
Design Challenge
Adopt a new verification environment to enable hardware/software co-verification
Speed development time for 6-million-gate Link Layer Processor

Cadence Solution
Demonstrated the power of the Cadence Palladium® accelerator/ emulator by bringing up a new verification environment in only two weeks
Success of initial project convinced Agere to choose the Incisive Palladium II system for future designs
 Read Full story»

Agilent Technologies
Chris Silsby
Agilent Technologies

Chris Silsby from Agilent Technologies talks about how the Virtuoso accelerated layout technologies help Agilent complete a variety of experiments in hours instead of weeks, and complete the project on schedule.

austriamicrosystems
Douglas Pattullo
austriamicrosystems

Douglas Pattullo talks about how the robust and stable technologies from the Virtuoso custom design platform help austriamicrosystems build design kits that facilitate fast, productive design to market.

Digeo
Toby Farrand
Digeo

Toby Farrand, Chief Technical Officer of Digeo talks about how Digeo and Cadence Engineerings Services collaborate to achieve first silicon success on X-Stream project.

Epoch Microelectronics
Design Challenge
Larger chips but shorter design cycles
Integrating an entire transceiver supporting multiple standards onto a single SoC

Cadence Solution
Integrated full-chip RF design and simulation methodology
Mixed-signal verification
 Read Full story »

Intrinsity
Tom Rudwick
Intrinsity

Tom Rudwick of Intrinsity talks about how the Virtuoso accelerated layout technologies, with its easy-to-use shape-based router, help Intrinsity to meet electromigration constraints and design to volume.

Realtek
Design Challenge
Shorter design cycles
Simulation of larger, more complex mixed-signal designs

Cadence Solution
Large-capacity design and verification based on known database structures
Mixed-signal verification using FastSPICE technology
 Read Full story »

Silansys Semiconductor
Niall O hEarcain
Silansys Semiconductor

Niall O hEarcain, the CEO of Silansys Semiconductor describes the benefits of partnering with Cadence for advanced RF level and multimillion-gate designs.

Silicon Labs
Business Challenge
  • Ramp up the company’s product development capabilities
Design Challenge
  • Create and implement efficient design flow and methodology, supported by single toolset, for development of low-energy MCUs
Cadence Solution
  • Integrated mixed-signal, low-power RTLto-signoff flow based on Cadence Assura, Encounter, Incisive, and Virtuoso platforms
Results
  • Saved several months in development time for design flows
  • 20 months after the start-up of the company, the first 32-bit MCU (EFM32 Gecko) was launched, consuming only a quarter of the energy of competing products
  • Developed new 32-bit MCU in just 4 months, saving up to 8 months of effort due to innovative design methodology and focus on re-usability
 Read full story»

Sipex
Steve Stern
Sipex

Steve Stern from Sipex talks about how the Virtuoso custom design platform and Cadence Engineering Services provided technologies and methodologies that reduced design cycle time from months to weeks and increased employee retention.

Teradyne
Design Challenge
Complex analog and mixed-signal SoC simulations
Wide variety of applications and test priorities

Cadence Solution
Token-based licensing model for flexible simulation solutions over a wide range of design verification requirements
Increased speed to market from a single testbench configuration directly integrated to the design process
 Read Full story »

Virage Logic
Ken Rousseau
Virage Logic

Ken Rousseau, VP Software Development of Virage Logic talks about how Virage Logic delivers memory compiler using high-performance, industry-standard Virtuoso custom IC layout.

Zeevo
Edwin Li
Zeevo

Edwin Li, Ph.D. from Zeevo talks about how the Virtuoso custom design platforms speeds the design of highly integrated Bluetooth SoC RF modules by enabling simulation of designs at real-time 2.4-gigahertz speed through the Virtuoso AMS Designer Simulator.

Saphyrion
Angelo Consoli
Saphyrion

Angelo Consoli, Managing Director at Saphyrion, details how they leverage the Cadence Virtuoso custom/analog flow and design services to develop ASICs High-End ground and space applications.