Chris Silsby from Agilent Technologies talks about how the Virtuoso accelerated layout technologies help Agilent complete a variety of experiments in hours instead of weeks, and complete the project on schedule.
Douglas Pattullo talks about how the robust and stable technologies from the Virtuoso custom design platform help austriamicrosystems build design kits that facilitate fast, productive design to market.
Toby Farrand, Chief Technical Officer of Digeo talks about how Digeo and Cadence Engineerings Services collaborate to achieve first silicon success on X-Stream project.
Tom Rudwick of Intrinsity talks about how the Virtuoso accelerated layout technologies, with its easy-to-use shape-based router, help Intrinsity to meet electromigration constraints and design to volume.
Niall O hEarcain
Niall O hEarcain, the CEO of Silansys Semiconductor describes the benefits of partnering with Cadence for advanced RF level and multimillion-gate designs.
- Ramp up the company’s product development capabilities
- Create and implement efficient design flow and methodology, supported by single toolset, for development of low-energy MCUs
- Integrated mixed-signal, low-power RTLto-signoff flow based on Cadence Assura, Encounter, Incisive, and Virtuoso platforms
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- Saved several months in development time for design flows
- 20 months after the start-up of the company, the first 32-bit MCU (EFM32 Gecko) was launched, consuming only a quarter of the energy of competing products
- Developed new 32-bit MCU in just 4 months, saving up to 8 months of effort due to innovative design methodology and focus on re-usability
Steve Stern from Sipex talks about how the Virtuoso custom design platform and Cadence Engineering Services provided technologies and methodologies that reduced design cycle time from months to weeks and increased employee retention.
Ken Rousseau, VP Software Development of Virage Logic talks about how Virage Logic delivers memory compiler using high-performance, industry-standard Virtuoso custom IC layout.
Edwin Li, Ph.D. from Zeevo talks about how the Virtuoso custom design platforms speeds the design of highly integrated Bluetooth SoC RF modules by enabling simulation of designs at real-time 2.4-gigahertz speed through the Virtuoso AMS Designer Simulator.
Watch this 2-minute video to hear Sorabh Sachdeva, a design engineer at Freescale Semiconductor, explain how he and his team used Cadence® Virtuoso® Schematic Editor to solve their verification challenges on their mixed-signal, low-power, multi-voltage SoCs.
In this video from CDNLive Silicon Valley 2014, Jurgen Hissen, principal engineer, MSCAD, at PMC discusses an aggressive RF design with distortion problems in the lab, and how a solution was developed in collaboration with Cadence® FAEs using Cadence Spectre® Accelerated Parallel Simulator's distortion summary feature. This solution provided improved visibility into circuit operation to speed up the distortion-sensitive design cycle by 30%, and more deterministic silicon performance leading to fewer disconnects between simulation and lab.
Angelo Consoli, Managing Director at Saphyrion, details how they leverage the Cadence Virtuoso custom/analog flow and design services to develop ASICs High-End ground and space applications.