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Cadence SiP Layout 


Advanced system-in-package implementation including die/BGA interface optimization

Cadence® SiP Layout provides a complete constraint- and rules-driven substrate layout environment, including full 3D design visualization, verification, and editing capabilities. Direct integration with Cadence OrbitIO™ Interconnect Designer provides the rapid implementation of proven interconnect pathways and die/BGA assignments.

Cadence SiP Design Datasheet »

  • Encounter and Virtuoso integration features integrated into a single product: Chip Integration Option for Cadence SiP Layout XL (available in January 2010)