Home > Tools > IC Packaging and Co-Design > Cadence SiP Layout > Resource Library

Cadence SiP Layout 


Advanced system-in-package implementation including die/BGA interface optimization

Cadence® SiP Layout provides a complete constraint- and rules-driven substrate layout environment, including full 3D design visualization, verification, and editing capabilities. Direct integration with Cadence OrbitIO™ Interconnect Designer provides the rapid implementation of proven interconnect pathways and die/BGA assignments.

Cadence SiP Design Datasheet »
6 resources found
 
Title Type Rated
Cadence SiP Layout WLCSP Option Datasheet
Format: .PDF    Date: 14 Mar 2016
Datasheet
 0
Recommend!
Cadence Fact Sheet
Format: .PDF    Date: 19 Feb 2016
Financial Report
 44
Recommend!
Cadence SiP Digital Design Datasheet
Format: .PDF (1.5MB)    Date: 14 Jul 2015
Datasheet
 2
Recommend!
Cadence RF SiP Methodology Kit Overview
Format: .PDF    Date: 01 Jun 2008
Datasheet
 3
Recommend!
Cadence SiP Design Datasheet
Format: .PDF (1.4MB)    Date: 01 Jun 2007
Datasheet
 2
Recommend!
Cadence RF Design Methodology Kit Datasheet
Format: .PDF    Date: 01 Feb 2007
Datasheet
 2
Recommend!