Home > Products > IC Packaging and SiP Design > Cadence SiP Digital SI > Resource Library

Email
* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Company Location *

Comments: *

Cadence SiP Digital SI 

Virtual high-speed interconnect simulation

Cadence SiP Digital SI offers a powerful simulation environment for source synchronous and serial interfaces. Integration with a 3D field solver resolves performance issues early and enables extensive post-layout debugging.

Cadence IC-Package Design Datasheet »
6 resources found
 
Title Type Rated
Cadence SiP Digital Design Datasheet
Format: .PDF (1MB)    Date: 14 Dec 2011
 		Datasheet
 0
Recommend!
Cadence RF SiP Methodology Kit Overview
Format: .PDF    Date: 01 Jun 2008
 		Datasheet
 2
Recommend!
Modeling and Analysis Methodologies of Complex Digital System-in-Package Designs
Format: .PDF (2.9MB)    Date: 15 Sep 2007
 		Conference Paper
 8
Recommend!
Automated Parasitic Backannotation and Testbench Generation for Verification of RF SiP Designs
Format: .PDF (3.3MB)    Date: 15 Sep 2007
 		Conference Paper
 2
Recommend!
Interview: SiP16.0 extends RFSiP Implementation to Parasitics/Simulation
Format: .PDF    Date: 18 Jul 2007
 		Release Information
 1
Recommend!
Cadence RF Design Methodology Kit Datasheet
Format: .PDF    Date: 01 Feb 2007
 		Datasheet
 2
Recommend!
Display  20 | 50      
All Cadence Resources »