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Cadence SiP Digital SI 

Virtual high-speed interconnect simulation

Cadence SiP Digital SI offers a powerful simulation environment for source synchronous and serial interfaces. Integration with a 3D field solver resolves performance issues early and enables extensive post-layout debugging.

Cadence IC-Package Design Datasheet »

Product ImageCadence® SiP Digital SI creates a simulation environment directly with the SiP design database to perform accurate signal prototyping and interconnect extraction without time-consuming setup and translation. A graphical topology simulator/editor allows engineers to compare different electrical routing strategies, optimize design rules, and develop S-Parameter models. Providing key indicators early in the design process helps make difficult cost/performance and physical/electrical design tradeoffs. Embedded integration with a partner supplied 3D field solver (contact Cadence for supported partners) provides complex geometry extraction for accurate interconnect simulation.

  • Reads/writes Cadence SiP Layout files
  • Streamlines virtual prototyping, interconnect exploration, analysis, and modeling
  • Provides fast, high-capacity simulation for multi-gigahertz interconnect analysis
  • Performs topology editing and solution space exploration
  • Includes SPICE-based simulation
  • Provides embedded integration with partner supplied 3D field solvers
  • Provides hierarchical constraint management
  • Enables virtual substrate editing and post-layout debugging
  • Simplifies design debug and reviews with Cadence 3D Design Viewer