Logical and physical co-design using 3D techniquesCadence SiP Digital Layout provides a complete constraint- and rules-driven co-design and substrate layout environment for SiP implementation, including full 3D creation and editing capabilities.
 Cadence SiP Digital Layout Datasheet » |
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 Cadence ® SiP Digital Layout is the physical co-design and place-and-route solution for complex 3D SiP package design. Supporting all package interconnect strategies and combinations, SiP Digital Layout provides constraint-driven layout of the package substrate. Since it must operate in a 3D world, SiP Digital Layout allows stack assembly optimization with 3D layout and editing. It also performs autoroute and breakout on flip-chip dies to reduce time-consuming and tedious manual breakout. Comprehensive DFM checking and modification improve substrate yield. Design review documentation and debug, followed by direct manufacturing tapeout, complete the package.
Features/Benefits
- Reads Encounter® digital IC design technology databases
- Includes embedded IC mask-ready I/O planning editor based on First Encounter® technology
- Provides 3D die stack creation/editing for rapid stack assembly and optimization
- Completes I/O padring/array co-design with multi-level optimization
- Enables connectivity assignment to minimize layer usage based on SI analysis
- Includes solid model 3D design viewer with snapshots for design review
- Performs 3D wirebond verification and DRC
- Supports bi-directional ECO and LVS flow for full co-design environment profiles
- Includes a comprehensive suite of DFM preparation technologies
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