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Cadence SiP Digital Architect

SiP concept authoring, prototyping, and design

Cadence SiP Digital Architect provides an environment for early design exploration, evaluation, and tradeoff using a co-design methodology from IC die to SiP substrate and target PCB system.

Cadence SiP Digital Architect Datasheet »

Encounter and Virtuoso integration features integrated into a single product: Chip Integration Option for Cadence SiP Layout XL (available in January 2010)

IC Packaging and SiP Design

IC Packaging and SiP Design Home Allegro Package Designer Allegro Package SI Cadence 3D Design Viewer Cadence RF SiP Methodology Kit Cadence SiP Co-Design Cadence SiP Digital Architect Cadence SiP Digital Layout Cadence SiP Digital SI Cadence SiP Layout Cadence Virtuoso SiP Architect