Home > Tools > IC Packaging and Co-Design > Cadence SiP Co-Design > Resource Library


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Company Location *

Comments: *

Cadence SiP Co-Design 

Optimize the chip-package interface

Cadence SiP Co-Design technology provides true integration with IC design in a physical co-design environment to help engineers make strategic tradeoffs earlier and with greater confidence.

Cadence Co-Design Datasheet »
1 resources found
Title Type Rated
Cadence Chip-Package-Board Co-Design Solution Datasheet
Format: .PDF (1.8MB)    Date: 12 Aug 2011