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Virtuoso SiP Architect 

Virtuoso-driven mixed-signal SiP logical design and verification

Cadence® Virtuoso® SiP Architect integrates with the Virtuoso Analog Design Environment to provide a single schematic and circuit simulation design flow for mixed-signal SiP designs.

Cadence SiP Design Datasheet »

Product Image Virtuoso SiP Architect provides a full-featured mixed-signal design flow and design-exploration environment for multiple-chip and discrete-component integration. As an integrated part of the Virtuoso mixed-signal chip design environment, Virtuoso SiP Architect provides full circuit simulation of multi-technology chips and the IC package substrate. It builds the package-level design as a simulation-capable schematic for handoff to Cadence SiP Layout.

  • Integrates with Virtuoso Analog Design Environment
  • Supports bi-directional ECO and LVS flow for full co-design implementation
  • Implements design from Virtuoso output to package-level SiP schematic
  • Automates circuit simulation testbench management
  • Optimizes I/Os at the die bump level with a package-driven flow