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Virtuoso SiP Architect 


Virtuoso-driven mixed-signal SiP logical design and verification

Cadence SiP RF Architect integrates with the Virtuoso Analog Design Environment to provide a single schematic and circuit simulation design flow for mixed-signal SiP designs.

Cadence Co-Design Datasheet »

Product Image Cadence® Virtusoso SiP Architect provides a full-featured mixed-signal design flow and design exploration environment for multiple chip and discrete component integration. Working directly with the Virtuoso® RF/analog chip design environment, Virtuoso SiP Architect provides full circuit simulation of multi-technology chips and the IC package substrate, including the characterization of embedded passive devices. It builds the package-level design as a simulation-capable schematic for hand-off to Cadence SiP Layout, and receives in return the substrate-level interconnect parasitic models for extensive post-route circuit simulation.

Features/Benefits
  • Integrates with Virtuoso Analog Design Environment
  • Develops pre-layout definition of embedded RF passive devices
  • Supports bi-directional ECO and LVS flow for full co-design implementation
  • Implements design from Virtuoso output to package-level SiP schematic
  • Automates circuit simulation testbench management and parasitic backannotation
  • Optimizes I/Os at the die bump level with a package-driven flow