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Home > Tools > IC Packaging and Co-Design > Cadence RF SiP Methodology Kit

Cadence RF SiP Methodology Kit 

Complete mixed-signal technology, tutorials, and best practices

The Cadence RF SiP Methodology Kit provides a complete SiP development platform along with the latest proven methodologies for RF and mixed-signal SiP design.

Cadence RF SiP Methodology Kit Datasheet »

The Cadence® RF SiP Methodology Kit contains everything needed to adopt and implement advanced package design techniques for mixed-signal SiPs.

Cadence SiP RF Architect provides a full-featured integrated design flow and simulation environment. Cadence SiP RF Layout performs substrate place-and-route, die stack creation, and package-level integration and optimization. Cadence SiP Digital SI contributes robust simulation, extraction, and editing. The Kit also includes complete representative designs for each of the application areas, a library of reusable components and simulation plans, and thorough tutorial examples on how to apply Cadence solutions.

Kit benefits
  • Integrates with Encounter® digital and Virtuoso® RF/analog design technologies
  • Creates integration flow from Virtuoso Analog Design Environment to package-level SiP design
  • Guides new users through complete how-to tutorials
  • Performs virtual prototyping, interconnect exploration, analysis, and modeling
  • Implements package place-and-route, optimization, validation, and tapeout
  • Manages inductor synthesis and passive component modeling
  • Provides fast, high-capacity simulation for multi-gigahertz digital analysis
  • Enables topology editing and solution space exploration
  • Provides hierarchical constraint management
  • Supports bi-directional ECO and LVS flow for full co-design implementation
  • Performs system-level functional, performance, and closed-loop verification
Kit contents
  • Provides a unified schematic and simulation environment for RF/analog design
  • Imports IC die footprints directly for I/O co-design at IC and substrate levels
  • Performs efficient die stack assembly, DRC, and SI analysis at the system level
  • Integrates digital SI analysis and interconnect extraction
  • Permits interactive editing of die-to-die and substrate interconnects
  • Includes a library of components, models, and simulation/verification plans
  • Demonstrates representative designs of passive components to full packages