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IC Packaging and SiP Design

Physical layout and co-design

SiP and complex IC package design requires seamless integration between chip and package. Cadence^® physical layout and co-design technology offers powerful modeling and simulation to enable informed design tradeoffs early.

Allegro Package Designer

Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die or side by side die designs.

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Cadence 3D Design Viewer

Provides 3D visualization and wirebond design rule checking (DRC) for IC packages. Enables collaborative markups in a solid model viewer to modify wirebond profiles.

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Allegro Package Designer

Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die or side by side die designs.

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Allegro Package SI

Delivers a virtual prototyping design and simulation environment for IC packages using accurate 3D simulation models. Direct read/write from the design database provides fast, accurate models for critical design decisions.

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Cadence 3D Design Viewer

Provides 3D visualization and wirebond design rule checking (DRC) for IC packages. Enables collaborative markups in a solid model viewer to modify wirebond profiles.

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Cadence RF SiP Methodology Kit

Teaches proven RF SiP design techniques with examples from concept to manufacturing. Provides a complete software solution set for RF/wireless applications. Accelerates learning and productivity.

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Cadence SiP Co-Design

Flexible chip-package co-design methodologies with supporting utilities allow for customizable co-design flows that meet the organizational challenges associated with collaboration between chip and package design teams that may be globally distributed.

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Cadence SiP Digital Architect

Enables experimentation at the initial design stages for maximum functional density and performance. Evaluates tradeoffs and provides co-design optimization of IC I/O padring/array. Optimized for co-design with Encounter Digital Implementation System.

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Cadence SiP Digital Layout

Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Includes 3D die stack creation/editing and comprehensive substrate DFM capabilities.

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Cadence SiP Digital SI

Integrates digital SI analysis and interconnect extraction using SPICE-based simulation and embedded integration of a third-party 3D field solver. Permits interactive editing of die-to-die and substrate interconnects.

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Cadence SiP Layout

Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die, side by side die, and stacked die designs and also provides the foundation for chip-package co-design with Encounter or Virtuoso.

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Cadence Virtuoso SiP Architect

Delivers a single schematic and simulation solution for RF/analog ICs and complex IC package substrates. Supports package substrate-level passive structures based on Pcell technology. Also enables chip-package co-design with Virtuoso.

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