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IC Packaging and Co-Design 

Press Releases
Cadence and TSMC Expand Collaboration Efforts on Integrated Design Flow for InFO Technology
Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production
Cadence Announces Availability of Complete IC Packaging Design and Analysis Solutions for Advanced Fan-Out Wafer-Level Chip Scale Packaging

Multi-Fabric Planning for Efficient PCB Design
3D packaging takes a key step forward as TSMC tapes out CoWoS chips
IC Package prototyping methodology estimates feasibility and cost

Design Automation Conference - DAC 2016
06/05/2016 - Austin
CDNLive Korea 2016
07/13/2016 - Seoul
CDNLive Japan 2016
07/15/2016 - The Yokohama Bay Hotel Tokyu

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