What’s New in IC Packaging and SiP 16.5?
Cadence® Allegro® and OrCAD® 16.5 is our most recent release and includes many exciting new features for IC packaging and SiP co-design. It is focused on addressing four key technology challenges that are driven by customers’ macro-level business goals and the need to manage miniaturization, design complexity, design life cycle, faster data throughput, and design chain concerns.
Allegro Package Designer and Cadence SiP – all tiers
- Wirebond design enhancements
- Easier access to color and visibility (on/off) control of specific wire profiles
- Symbol spreadsheet export
- Color-coded spreadsheet output (XML) representative of package footprint netlist or die netlist
- Embedded component support
- Components (die or passives) may now be placed on inner layers of the package substrate
- Usability improvements
- Enhancements to net color/highlighting
- Enhanced highlighting and dimming features
- Common pin/finger highlight command
- Set color based on various objects and how they are used (e.g. bond finger alignment)
- Dynamic “shape-based” fillets on cline width transitions
- New symbol (die or BGA) editor app mode
Cadence SiP Layout XL, or Allegro Package Designer licensed with Cadence SiP Layout XL
- Route planning
- Plan your routing paths for interfaces with Interface Flow Designer (IFD)
- Improved Assembly rule checking for APD / SiP Layout
- Assembly Rule Checks in APD or SiP Layout includes new DRC codes for violations
- 3D Viewer integration enhancements
- Multi-net highlighting in 3D viewer
Co-design options for Cadence SiP Layout XL
- Distributed co-design with Virtuoso® and Encounter® environments
- Die abstract exchange between SiP Layout and either Virtuoso Digital Implementation or Encounter Digital Implementation (EDI) System
- Special options enable:
- Language-based rule checking
- RDL route exchange between chip and package