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IC Packaging and Co-Design 

16.6-2015 16.6 Release 16.5 Release
Allegro ADP/SIP 16.6 Quarterly Incremental Report »

What’s New in IC Packaging 16.6-2015?
Our latest release, Cadence® Allegro® and OrCAD® 16.6-2015, includes many new features for IC packaging and system-in-package (SiP) IC/package/PCB cross-substrate interconnect design and optimization.

Allegro Package Designer (APD) and Cadence SiP Layout
  • Dedicated metal fill/pour/edit application mode for improved usability and designer productivity
    • Improved boundary editing. Context menu or single-pick execution mode command access for slide edges with corners, chamfer/round corners, join edges, add notches, and multi-segment movement.
      Figure 1. ShapeApp mode makes it easy to edit complex shapes quickly
  • Productization of previous beta/eval features
    • Variant-based design
    • Netlist export
    • Degassing
    • Replacement of via with via array
  • Package integrity rule that reports metal connected by overlap but not by database connectivity
Cadence SiP Layout or Allegro Package Designer Using a Cadence SiP Layout License
  • Die Abstract Refinement Editor
    • Improves performance when read/writing a die abstract
    • Reduces ECO time between package team and IC team when optimizing co-design die bump locations
  • Custom (user-defined) DRC rules checking engine
    • Custom “batch” DRC rules can be written using the optional rules developer toolkit
    • Custom DRCs report errors graphically and show them in Constraint Manager
  • Ability to add ground current return path vias to differential pairs during Add Connect. You can select from one of many configurations supported with parameters.
    Figure 2. Ground current return path via structures available for differential pairs during Add Connect
    • Adjust spacing: During route engine-assisted auto-connect routing, you can compress spreading of traces in the trunk of a set of signals. It will also nudge/push existing traces.
    • Snake routing improvements for fine-pitch BGAs allow you to route quickly, easily, and with ability to restart from a previously routed path
    Figure 3: Snake routing
    • Off-angle routing
    • You can now very quickly create off-angle routes to avoid FR4 fiber weave coupling and achieve better impedance control
    Figure 4: Fabric weave zig-zag routing
    • Auto-interactive Phase Tuning (AiPT) now supports bumps on off-angle routes
    • Improved arc support in routing
    • Improved support for push-n-shove with arcs
    • AiPT arcs on tuning bumps
    • Auto-interactive Delay Tuning (AiDT) supports arcs on tuning bumps
Cadence Advanced Package Router (APR)
  • Performance improvements and improved Quality Of Results
Cadence OrbitIO interconnect designer
  • Full product support for six methodology use models
    • PCB-driven BGA ball map (Watch Demo Video)
      • Optimizes a BGA and IC bump array to a reference PCB
      • Creates an updated PCB footprint and a schematic symbol for Allegro Design Entry HDL
    • IC-driven ball map (Watch Demo Video)
      • Creates and optimizes a package BGA ball map based on an existing IC bump array
    • Multi-substrate interconnect (Watch Demo Video)
      • Optimize across an IC bump array, package BGA ball map, and a PCB breakout
    • Standalone ball map (Watch Demo Video)
      • Rapid start-from-nothing creation of an initial package BGA ball map
    • BGA-driven IC bump array
      • Drive the creation and optimization of an IC bump array based on a package BGA ball map
    • BGA ball map based on PCB variants
      • Optimized a package BGA ball map so it will work across a number of PCB designs
    • Increased accuracy of Feasibility Router
      • Higher level of implementation certainty from developed pathways
      • Increases user confidence in designed pathways
What’s New in IC Packaging and SiP 16.6?
Our latest release, Cadence® Allegro® and OrCAD® 16.6 includes many exciting new features for IC packaging and system-in-package (SiP) co-design. It addresses key technology challenges driven by our customers’ macro-level business goals and the need to manage miniaturization, design complexity, design life cycle, faster data throughput, and design chain concerns. The 16.6 release also integrates Sigrity technologies for enhanced signal/power integrity analysis and package design capabilities.

Allegro Package Designer and Cadence SiP – all tiers
  • New wirebond application mode reduces menu picks and accelerates design creation
  • New Open Cavity database object enables placement of die below the substrate surface, allowing you to create low-profile IC packages
  • Wafer-level chip-scale-package (WLCSP) flow enhanced through GDSII in/out improvements
  • New option for integrated Advanced Package Router (Sigrity technology)
  • New options for integrated signal integrity and power integrity signoff flows (Sigrity technology)
Cadence SiP Layout XL, or Allegro Package Designer licensed with Cadence SiP Layout XL
  • 3D Viewer enhancements enable visualization of package mold cap
What’s New in IC Packaging and SiP 16.5?
Cadence® Allegro® and OrCAD® 16.5 is our most recent release and includes many exciting new features for IC packaging and SiP co-design. It is focused on addressing four key technology challenges that are driven by customers’ macro-level business goals and the need to manage miniaturization, design complexity, design life cycle, faster data throughput, and design chain concerns.

Allegro Package Designer and Cadence SiP – all tiers
  • Wirebond design enhancements
    • Easier access to color and visibility (on/off) control of specific wire profiles
  • Symbol spreadsheet export
    • Color-coded spreadsheet output (XML) representative of package footprint netlist or die netlist
  • Embedded component support
    • Components (die or passives) may now be placed on inner layers of the package substrate
  • Usability improvements
    • Enhancements to net color/highlighting
      - Enhanced highlighting and dimming features
      - Common pin/finger highlight command
      - Set color based on various objects and how they are used (e.g. bond finger alignment)
    • Dynamic “shape-based” fillets on cline width transitions
    • New symbol (die or BGA) editor app mode
Cadence SiP Layout XL, or Allegro Package Designer licensed with Cadence SiP Layout XL
  • Route planning
    • Plan your routing paths for interfaces with Interface Flow Designer (IFD)
  • Improved Assembly rule checking for APD / SiP Layout
    • Assembly Rule Checks in APD or SiP Layout includes new DRC codes for violations
  • 3D Viewer integration enhancements
    • Multi-net highlighting in 3D viewer
Co-design options for Cadence SiP Layout XL
  • Distributed co-design with Virtuoso® and Encounter® environments
    • Die abstract exchange between SiP Layout and either Virtuoso Digital Implementation or Encounter Digital Implementation (EDI) System
    • Special options enable:
      - Language-based rule checking
      - RDL route exchange between chip and package