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IC Packaging and SiP Design
Physical layout and co-design
SiP and complex IC package design requires seamless integration between chip and package. Cadence
®
physical layout and co-design technology offers powerful modeling and simulation to enable informed design tradeoffs early.
Allegro Package Designer
Integrates advanced package design with concurrent IC development. Analyzes physical, electrical, and cost tradeoffs early. Optimizes connectivity, routing, and SI using a constraint-driven methodology.
Learn more
»
Cadence 3D Design Viewer
Provides 3D visualization and wirebond design rule checking (DRC) for IC packages. Enables collaborative markups in a solid model viewer to modify wirebond profiles.
Learn more
»
SI analysis and modeling
Signal integrity and package characterization are essential to evaluate design impact on system performance. Cadence
®
technology provides integrated SI analysis, modeling, and simulation to verify design quality while controlling schedule and cost.
Allegro Package SI
Delivers a virtual prototyping design and simulation environment for IC packages using accurate 3D simulation models. Direct read/write from the design database provides fast, accurate models for critical design decisions.
Learn more
»
Cadence SiP Digital SI
Integrates digital SI analysis and interconnect extraction using SPICE-based simulation and embedded integration of a third-party 3D field solver. Permits interactive editing of die-to-die and substrate interconnects.
Learn more
»
Cadence RF SiP Methodology Kit
Teaches proven RF SiP design techniques with examples from concept to manufacturing. Provides a complete software solution set for RF/wireless applications. Accelerates learning and productivity.
Learn more
»
Digital SiP design
SiP development requires co-design directly with chip teams based on the connectivity-authored interconnect strategy. Cadence
®
solutions provide I/O optimization, tradeoff simulation, and constraint-driven implementation.
Cadence SiP Digital Architect
Enables experimentation at the initial design stages for maximum functional density and performance. Evaluates tradeoffs and provides co-design optimization of IC I/O padring/array.
Learn more
»
Cadence SiP Digital Layout
Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Includes 3D die stack creation/editing and comprehensive substrate DFM capabilities.
Learn more
»
Cadence SiP Digital SI
Integrates digital SI analysis and interconnect extraction using SPICE-based simulation and embedded integration of a third-party 3D field solver. Permits interactive editing of die-to-die and substrate interconnects.
Learn more
»
Analog and RF SiP design
Mixed-signal applications in hand-held devices drive SiP design, but RF integration complicates performance. Cadence
®
analog and RF SiP design begins with chip design data and enables package-level simulation, optimization, and verification.
Cadence SiP RF Architect
Delivers a single schematic and simulation solution for RF/analog ICs and complex IC package substrates. Supports package substrate-level passive structures based on Pcell technology.
Learn more
»
Cadence SiP RF Layout
Provides a complete constraint- and rules-driven substrate layout and 3D interconnect environment. Enables extensive post-route parasitic extraction, including substrate-level passive network structures.
Learn more
»
Cadence RF SiP Methodology Kit
Teaches proven RF SiP design techniques with examples from concept to manufacturing. Provides a complete software solution set for RF/wireless applications. Accelerates learning and productivity.
Learn more
»
Allegro Package Designer
Integrates advanced package design with concurrent IC development. Analyzes physical, electrical, and cost tradeoffs early. Optimizes connectivity, routing, and SI using a constraint-driven methodology.
Learn more
»
Allegro Package SI
Delivers a virtual prototyping design and simulation environment for IC packages using accurate 3D simulation models. Direct read/write from the design database provides fast, accurate models for critical design decisions.
Learn more
»
Cadence 3D Design Viewer
Provides 3D visualization and wirebond design rule checking (DRC) for IC packages. Enables collaborative markups in a solid model viewer to modify wirebond profiles.
Learn more
»
Cadence RF SiP Methodology Kit
Teaches proven RF SiP design techniques with examples from concept to manufacturing. Provides a complete software solution set for RF/wireless applications. Accelerates learning and productivity.
Learn more
»
Cadence SiP Digital Architect
Enables experimentation at the initial design stages for maximum functional density and performance. Evaluates tradeoffs and provides co-design optimization of IC I/O padring/array.
Learn more
»
Cadence SiP Digital Layout
Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Includes 3D die stack creation/editing and comprehensive substrate DFM capabilities.
Learn more
»
Cadence SiP Digital SI
Integrates digital SI analysis and interconnect extraction using SPICE-based simulation and embedded integration of a third-party 3D field solver. Permits interactive editing of die-to-die and substrate interconnects.
Learn more
»
Cadence SiP RF Architect
Delivers a single schematic and simulation solution for RF/analog ICs and complex IC package substrates. Supports package substrate-level passive structures based on Pcell technology.
Learn more
»
Cadence SiP RF Layout
Provides a complete constraint- and rules-driven substrate layout and 3D interconnect environment. Enables extensive post-route parasitic extraction, including substrate-level passive network structures.
Learn more
»
Content Query Web Part [2]
Check out the latest exciting webinars offered in the Allegro Summer Webinar Series
New Cadence Design Technology Tackles Miniaturization, Product Design and Low-Power Challenges for IC Package/SiP Designers
New 2009 Allegro and OrCAD webinars winter/spring series
speakTECH Feeder Viewer for Community Server
Recent Blog Posts
APD and SiP Layout 16.3 - Virtual-ly Amazing
Everything You Want to Know About APD / SiP 16.2 - Bill Acito Webinar on March 18
Brad Griffin Speaks at DesignCon - Give Him a Listen!!
Visit the Community
»
Content Query Web Part [3]
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