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IC Packaging and Co-Design 





Physical Implementation
Complexity and performance requirements of today’s semiconductor packages continue to increase while design resources remain static for most organizations - placing a premium on efficiency and productivity. Cadence package implementation products deliver the automation and accuracy to expedite the design process as part of a comprehensive environment including analysis and co-design.

Cadence SiP Layout
Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die, side by side die, and stacked die designs and also provides the foundation for chip-package co-design with Encounter or Virtuoso.
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Allegro Package Designer
Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die or side by side die designs.
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Advanced Package Router
Breakthrough auto-routing technology specifically for high-performance flip-chip packages that reduce design cycle-time and increase designer efficiency.
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Cadence 3D Design Viewer
Provides 3D visualization and wirebond design rule checking (DRC) for IC packages. Enables collaborative markups in a solid model viewer to modify wirebond profiles.
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