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IC Packaging and SiP Design 

Bayside Design Inc
Design Challenge
Develop a complete evaluation system for 6.5-Gbps SerDes design, including package, board, FPGA, and software for debug
Complete project in eight weeks

Cadence Solution
Upgraded design environment with Cadence Allegro® system interconnect design platform
 Read Full story »

VeriSilicon
Design Challenges
Accelerate the design process with automated, placement-aware pin assignment
Optimize the physical connectivity, even as it changes
Ensure quality and reduce complexity with reuse of interface rules and protocols

Cadence Solution
Allegro FPGA System Planner XL
 Read Full story»

Open-Silicon, Inc.
Kavitha Nagarajan
Open-Silicon, Inc.
Kavitha Nagarajan, Lead Engineer – IC Package Design at Open-Silicon, Inc., describes how the company leveraged the Cadence Integrated SPB environment to successfully complete a complex project with a tight deadline.