Bayside Design Inc
Dialog Semiconductor faced a potentially daunting challenge: reduce the size and cost of its PCBs via embedded passive devices at the substrate level. The company needed a tool that could help migrate from a two-layer BGA substrate to four layers. Rajesh Aiyandra, package design and simulation team leader at Dialog, explains how Cadence SiP Digital Layout helped deliver a smooth migration, from the change in the number of layers to the change in the via specifications.
- Produce prototype of highly complex, 300-million-gate SoC—the 1st such effort in Taiwan—in 7 months
- Grow business through ability to develop large-scale chip designs
- Shorten verification and analyses processes
- Process large database for huge SoC design
- Manage and integrate different technologies across industries
- First Encounter® Design Exploration and Prototyping
- Encounter® Digital Implementation System
- Encounter Conformal® Equivalence Checker
- Incisive® verification platform
- Sigrity™ packaging and PCB signal and power analysis solutions
- Verification IP Catalog
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- Completed complex design from data-in to tapeout within 7 months
- Reduced one iteration for timing optimization, extraction, analysis and verification of physical design down to 4 days
- Expanded design capacity by 10X
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