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IC Packaging and Co-Design 

Bayside Design Inc
Design Challenge
Develop a complete evaluation system for 6.5-Gbps SerDes design, including package, board, FPGA, and software for debug
Complete project in eight weeks

Cadence Solution
Upgraded design environment with Cadence Allegro® system interconnect design platform
 Read Full story »

VeriSilicon
Design Challenges
Accelerate the design process with automated, placement-aware pin assignment
Optimize the physical connectivity, even as it changes
Ensure quality and reduce complexity with reuse of interface rules and protocols

Cadence Solution
Allegro FPGA System Planner XL
 Read Full story»

Dialog Semiconductor
Rajesh Aiyandra
Dialog Semiconductor

Dialog Semiconductor faced a potentially daunting challenge: reduce the size and cost of its PCBs via embedded passive devices at the substrate level. The company needed a tool that could help migrate from a two-layer BGA substrate to four layers. Rajesh Aiyandra, package design and simulation team leader at Dialog, explains how Cadence SiP Digital Layout helped deliver a smooth migration, from the change in the number of layers to the change in the via specifications.

Faraday Technology
Business Challenge
  • Produce prototype of highly complex, 300-million-gate SoC—the 1st such effort in Taiwan—in 7 months
  • Grow business through ability to develop large-scale chip designs
Design Challenges
  • Shorten verification and analyses processes
  • Process large database for huge SoC design
  • Manage and integrate different technologies across industries
Cadence Solutions
  • First Encounter® Design Exploration and Prototyping
  • Encounter® Digital Implementation System
  • Encounter Conformal® Equivalence Checker
  • Incisive® verification platform
  • Sigrity™ packaging and PCB signal and power analysis solutions
  • Verification IP Catalog
Results
  • Completed complex design from data-in to tapeout within 7 months
  • Reduced one iteration for timing optimization, extraction, analysis and verification of physical design down to 4 days
  • Expanded design capacity by 10X
 Read full story»

FTD Automation
Mahendra
FTD Automation

FTD Automation is a Cadence® channel partner in India. In this video, Mahendra, a Sr. applications engineer at FTD Automation, talks about the time-to-market and scalability benefits of Cadence OrCAD® PCB design tools. These tools, says, Mahendra, help design engineers address challenges including design complexity and cost, with capabilities including fully integrated schematic entry, signal integrity analysis, and place-and-route methodology.

Hyundai MOBIS
Imran Shaik
Hyundai MOBIS

Automotive parts manufacturer Hyundai MOBIS was facing electromagnetic interference (EMI) problems with its PCB designs. In this short video clip, Imran Shaik, a project lead on EMI simulations, discusses how Cadence® Sigrity™ PowerSI™ and Cadence Sigrity SPEED2000™ helped the company reduce its PCB testing time and get its products to market faster.

Lattice
Maryam Shahbazi
Lattice

Lattice is a global leader in delivering ultra-low power FPGAs for manufacturers of smartphones, small cell networking equipment, and industrial applications. For its customer base, fast time to market, low power, and low cost are important considerations. In this video, Maryam Shahbazi of Lattice's Systems Development Group talks about how the company relies on Cadence® Sigrity™ tools to model its power delivery network, solve power integrity issues, and improve voltage margins.

Open-Silicon, Inc.
Kavitha Nagarajan
Open-Silicon, Inc.

Kavitha Nagarajan, Lead Engineer – IC Package Design at Open-Silicon, Inc., describes how the company leveraged the Cadence Integrated SPB environment to successfully complete a complex project with a tight deadline.