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Advanced Package Router 



Cadence® Advanced Package Router (APR) was developed specifically to address the high-speed constraints and geometrical challenges of flip-chip packages. APR employs a topological route methodology supported by advanced algorithms that produce quality results while significantly reducing route time. APR is available as an option to either Cadence APD or SiP.
Performance and complexity of modern flip-chip packages is fueled by demand for greater functional density, bandwidth, and speed, which is made possible by today’s silicon process technologies. Resulting flip-chip designs may contain upwards of 10,000 connections with 50% to 75% of the nets having high-speed constraints, such as differential pairs or timing rules. These designs may take up to three months to complete with 85% of that time allocated to routing. It’s not uncommon for two to three major design revisions to take place requiring partial or complete re-routing.

APR is focused on automating the increasingly complex and time-consuming task of flip-chip routing. However, automation requires new technology and algorithms that are package-centric and not re-purposed PCB route technology. APR employs a topological route methodology that enables quick evaluation of numerous route scenarios before converging on a final solution. Features like complex via generation, dynamic push and shove, and high-speed constraint-aware routing produce high-quality results and completion rates with minimal cleanup needed.

Features
  • Full multi-layer utilization and path searching with dynamic via generation
  • Automatic generation of complex via structures such as stagger, spiral, and stair step
  • Works with pre-existing traces or automatically generated bump escape routes
  • Simultaneous fan-out routing of signal, power, and ground connections
  • Robust squeeze and push capability for high-density results
  • Region-based constraint support
  • Fan-in-capable routing to maximize use of space
Benefits
  • Significantly shortens design cycle time of complex flip-chip packages
  • Provides high-quality results and completion rates with minimal need for clean-up
  • Automates time-intensive tasks to improve efficiency and throughput
  • Uses high-speed constraint-aware routing for electrically correct results
  • Simplifies setup and execution directly from APD or SIP