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Cadence 3D Design Viewer 

Solid model IC package viewing and wirebond DRC

Cadence® 3D Design Viewer allows IC package engineers to interact with an accurate 3D model of the physical design and conduct comprehensive wirebond design rule checking.

Cadence 3D Design Viewer Datasheet »

Physical Layout and Co-Design
  • New Product SiP Layout XL
    • Cost-effective Windows-based solution, preferred OSAT platform
      • supports Linux and UNIX as well
    • Allows for a distributed approach to co-design by using “die abstract” ECO files
      • Visibility of the chip IO pad ring and bump matrix within the SiP editing canvas
    • SiP Layout license also allows user to run Allegro® Package Designer (APD) software for ultimate flexibility
  • Interoperability between SiP Layout and Allegro Package Designer with new SiP Finishing Mode
    • Provides design-chain manufacturing preparation and editing of SiP designs
    • Protects/preserves chip stacking, bonding or co-design information/IP
    • Only allows substrate cleanup preparation for manufacture
    • Provides maximum openness and flexibility for SiP users
  • Wirebonding improvements
    • Non standard wire connections supports leadframe wirebonding
  • Routing improvements
    • Pad entry rules allows routing into bond fingers
    • Route off a finger at any angle
    • Wirebond finger stubs in either inward or outward direction stay aligned to bond finger
  • Package-driven co-design
    • Exchange die abstract files with Encounter Digital Implementation (EDI) tools
  • Assembly Rule Check improvements
    • Integrated with Constraint Manager
      • Singe user interface
      • Easy import / export of rules through technology file
  • Chip Integration Option for Cadence SiP Layout XL (available in January 2010)
    • Encounter and Virtuoso integration features integrated into a single product