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Allegro PCB Designer 


Constraint-driven PCB design

Cadence® Allegro® PCB Designer quickly takes simple or complex designs from concept to production in a constraint-driven design system. Its scalable based plus options model allows designers to cost-effectively match the technological and methodological needs of small to large companies and projects.

Allegro PCB Designer Datasheet »
Allegro PCB Designer Manufacturing Option Datasheet »
Allegro PCB RF Option Datasheet »
17.2-2016 Release 16.6 Release 16.6-2015 Release 16.5 Release
Allegro PCB Designer 17.2-2016 Release

The Allegro® 17.2-2016 release enables a more predictable and shorter design cycle. The portfolio features comprehensive in-design inter-layer checking technology that minimizes design-check-redesign iterations and a new dynamic concurrent-team-design capability that accelerates product creation time by up to 50 percent. Utilizing material inlay fabrication techniques, these new capabilities can reduce material costs by up to 25 percent. In addition, embedded Sigrity™ technology now ensures critical signals meet performance criteria and power integrity (PI) for PCB designers addressing power delivery and IR drop issues efficiently, eliminating time-consuming iterations with PI experts.

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Allegro PCB Designer (16.6 release)
  • Support for embedding components with dual-sided contacts and vertical components on the inner layers of a PCB
  • New embedded cavity DRCs
  • Faster timing closure with auto-interactive route delay tuning (AiDT)
  • PCB Team Design Option accelerates design implementation
    • Users can edit constraints and move components outside their design partition (flexible boundaries) without having to merge and split
    • An ECO wizard helps import netlist changes into design partitions
  • Auto-interactive pin-swap (“Planning Mode”) for FPGAs within Allegro PCB Editor using Allegro FPGA System Planner under-the-hood
  • Offset routing allows users to route off-orthogonal angles to avoid coupling high-speed signals with substrate glass fiber-weaves
  • New Slide function
    • New auto-join option during Slide simplifies the process of editing (orthogonal / off-angle) etch
    • Ability to slide segments with corners (three-segment slide)
    • Slide vertex preserves segment angles
  • DFM
    • Export / import design data to and from manufacturing using the open industry-standard IPC-2581
  • New artwork control form allows users to assign film record classes and subclasses to a film record
  • Additional ease-of-use and productivity improvements
    • General Edit Application Mode allows users to assign a single region constraint to multiple region shapes
    • Align components by edge (top, center, bottom) using DFA constraints or equal spacing (controllable by user-defined equal spacing and + and - buttons)
    • Support for text in Place Replicate
    • Quickplace allows component overlap (user-defined % overlap) to get the components on the board faster
    • Refresh a symbol by instance
    • New command allows users to add rectangles with parameterized corners (champhered, rounded, or orthogonal)
    • Dynamic shape allows thermal width for cross-hatch shapes based on the cross-hatch line width
    • New display option overlays net names along cline path, pins, shapes, and flow lines
    • Lines and text can now be moved outside their present class-subclass structure
    • Select objects by “Lasso” or “path”
    • Highlight or de-highlight nets associated with a component
    • DRC can now be run “by window” when online DRC is turned off
    • Specify any text for the associative dimension value using the optional Text filed in the Options tab
    • Specify separate output files for plated versus non-plated (NC) routing
    • Pastemask-to-pastemask DRC will check the “Package Geometry - Pastemask_Top” shapes within the same symbol
Allegro PCB RF Option
  • Improvements to importing from Agilent ADS to Allegro Design Authoring
    • Complex If …then.. elseif…elseif… expressions/equations support
    • Parasitic component import support
    • Import schematic as a block
    • Use same RefDes as in ADS including name, font size, and location
  • Support for new ADS RF etch elements libraries
    • VIA2 (cylindrical via hole in Microstrip)
    • SLINO
  • Snap improvements
    • Snap to any edge of a pad
    • Snap to a group
  • “Add Connect” allows users to connect to the edge of a pad, or overlapping a pad
  • Scaled copy allows snap to pad edge
  • Unnecessary DRC errors removed on netlist is imported into Allegro PCB Editor
  • Via exchange between ADS and Allegro environment

What's New in 16.5 Allegro PCB Design
Allegro PCB Editor
  • Front-to-back flow support for embedded packaged components
    • Supports traditional direct-attach as well as new indirect-attach methods
    • Provides support for open/closed cavities
    • Enables a constraint-driven embedded component design with constraints coming from design intent as well as from the targeted manufacturing approach (direct/indirect, etc.)
  • ECAD-MCAD co-design with ProStep EDMD Schema
    • Incremental design data exchange
    • Accept/reject for each change at object level
    • Notes/history
    • Review changes before accepting
  • Interconnect Flow Designer
    • Hierarchical route planning through bundle creation
    • Assign layers to bundles
    • Create “flow” plans for bundles
  • Use “rakes” to view rat-crossings easily
  • Intelligent PDF output
    • Produces Allegro board data in PDF with intelligent data for components, nets, and test points
    • Users can specify what graphical class/subclass layers may be viewed and what properties are to be extracted (see Allegro Design Publisher below)
  • Associative dimensioning
  • New differential phase tuning eliminates slow approach of tuning differential pairs to meet static or dynamic phase conditions
  • Dynamic trace tapering allows trace width changes across constraint-regions or on simple neck-downs
  • Group route via patterns for easy transition to different layers during multi-line routing
      
    • Differential pair transitions at region boundary provide symmetrical gathering at the boundary when crossed orthogonally or at 45 degrees
    • High-density interconnect (HDI) via-to-via line-fattening control option runs on selected clines
  • Delete unnecessary via structures from design database
  • Highlighting with stipple patterns
  • Separate dynamic and static shape display restored
  • Identify fixed elements with stipple pattern overlays
  • Data tip setup has been expanded to 17 entries
  • Placement using dynamic Design For Assembly (DFA) is now available in Allegro PCB Designer and supports side-end and end-side as distinct rules
  • Placement using dynamic DFA allows users to place components easily with minimum DFA clearance
  • Design for fabrication (DFF)
    • Minimum metal-to-metal clearance support to ensure minimum metal-to-metal clearance is met
  • Duplicate drill check detects duplicate drill holes spanning the same layers
  • Duplicate drill holes may be based on the same or different pad stack definitions
  • Backdrill capability now supports “any layer”-to-“any layer” configurations
  • Cumulative max neck length check
  • Database locking
    • Multi-threading DRC update now takes advantage of up to 16 processor cores running on the same machine
Allegro Design Publisher
  • Publishes Allegro board data in PDF
  • Exports reference designators, component properties, netnames, net properties, and test point data
  • Provides document controls such as options to reduce file size, maximize password security, and minimize property output
Allegro Analog / RF PCB Design
  • Context-sensitive RF PCB design
  • Custom shape import/export from/to Agilent ADS
  • Import hierarchical components in schematics from Agilent ADS
  • Insert a transmission line between two lines
  • Taper a transmission line
Allegro PCB Router
  • Performance improvements
  • Quality of routs (QoR) improvements for differential pairs
  • Alignment of rules with Allegro PCB Editor for HDI rules, inset vias, tangent vias
  • Support for embedded packaged components
  • Acid trap control for micro-vias that are tangent to a core via (automatic line fattening)
  • Via-list prioritization synchronized with setting in Allegro PCB Editor
Allegro Design Planning Option
  • Feasibility analysis and feedback for route plans created using Interconnect Flow Designer
  • Create “spatial” plans using the route engine
  • Convert “spatial” plans to traces (CLINES) quickly