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Allegro What's New 

17.2–2016 Release 16.6–2015 Release 16.6 QIR 7 16.6 QIR 5 16.6 Release 16.5 Release
The Cadence® Allegro® 17.2-2016 release enables a more predictable and shorter design cycle. The portfolio features comprehensive in-design inter-layer checking technology that minimizes design-check-redesign iterations and a new dynamic concurrent-team-design capability that accelerates product creation time by up to 50 percent. Utilizing material inlay fabrication techniques, these new capabilities can reduce material costs by up to 25 percent. In addition, embedded Sigrity™ technology now ensures critical signals meet performance criteria and power integrity (PI) for PCB designers addressing power delivery and IR drop issues efficiently, eliminating time-consuming iterations with PI experts.

New Allegro PCB Editor Capabilities

New capabilities for flex and rigid-flex designs
  • Stack-Up by Zone for Flex and Rigid-Flex Designs
    Multiple zones can be created using the new Cross-Section Editor to represent rigid-flex-rigid PCBs. The stack-up by zone feature provides faster, easier definition of stack ups for rigid-flex-rigid designs and improves MCAD-ECAD co-design.
  • Inter-Layer Checks for Rigid-Flex Design
    The Allegro PCB Editor 17.2-2016 release introduces new in-design inter-layer checks for flex and rigid-flex that save manual effort and ensure all rules for advance flex designs are adhered to, avoiding many design-check-redesign iterations.
  • Enhanced Contour, Arc-Aware Routing
    Enhanced Contour is a more efficient method to add routing during Add Connect by following an existing connect line or a route keep-in, which will save time for PCB designers working on flex designs.
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Cross-Section Editor
The Cross-Section Editor has been redesigned, leveraging the underlying spreadsheet technology found in Constraint Manager. It offers one-stop shop for features that require the cross section for their setup, such as dynamic unused pad suppression and embedded component design.

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Dynamic concurrent team design
The New Allegro dynamic concurrent-team-design capability focuses on shortening the largest portion of the PCB layout design cycle. It provides dynamic concurrent PCB team design for multiple PCB designers to work on the same design at the same time without any set-up requirements. In addition, new features—including interactive etch-editing capabilities, Allegro TimingVision™ technology, auto-interactive delay, and phase-tuning capabilities—provide proven time reductions to route advanced high-speed interfaces such as DDRx and PCI Express® (PCIe®) by up to 80 percent.

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New Padstack Editor
A new Padstack Editor eases padstack creation through a new modern user interface. New features include the padstack designer, padstack usage types, pad geometries, and several new drill features.

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Expanded in-design rules for backdrill vias
Many improvements have been made to the backdrill process to assist PCB designers in managing the backdrill vias/padstacks, route around the backdrill vias/padstacks with accurate DRCs, and real-time feedback.

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Tabbed routing
Tabbed routing is a new routing strategy in which trapezoidal shapes called tabs are added to parallel traces to control impedance in the pin-field/breakout region and crosstalk in open-field region. This method enables longer trace lengths and use of smaller trace spacing. Tabbed routing is used for impedance control and to manage crosstalk in critical signals, enhancing signal quality and improving route channel utilization.

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Return path management through custom via structures
The Allegro 17.2-2016 release enhances the six via structures for managing return paths for critical differential signals during Add Connect by allowing users to create using Allegro PCB Editor, validate using proven Sigrity technology, and instantiate a custom return path via structure during Add Connect.

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Ease-of-use improvements in Allegro PCB Editor
  • Visibility Pane—Access to Mask Layers and Zones
    The Visibility Pane has been enhanced to allow designers access and control of layer content more quickly and more efficiently.
  • Shape Edit Application Mode
    The Shape Edit Application Mode is a tuned editing environment primarily designed to increase efficiency with shape boundary editing.
  • Constraint Manager Improvements
    Many ease-of-use and productivity improvements have been made to Allegro Constraint Manager.
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New Allegro Front-End Design Capabilities

Support for watermark in generated PDF file in Allegro Design Authoring DE-HDL
Users can now embed a watermark such as “First Prototype,” “Confidential,” or “Review Copy” in the generated PDF file.

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Tag-based ECSet mapping in Allegro Design Authoring DE-HDL
ECSet nodes now support tags (pin parameter), which can be used to uniquely identify a pin and remove any ambiguity.

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Port Groups in Allegro Design Authoring DE-HDL
Net Groups can be pushed across different levels of hierarchy by creating a Port Group. The Port Group is made available to higher-level blocks through the hierarchical block symbol where they appear with a new Pin Shape for unique identification.

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Import of pin delay properties in front end in Allegro Design Authoring DE-HDL
A new DE-HDL console command is now provided to import a file containing the pin delay values that can be used to define the complete delay for pin pairs. The format of this file is exactly the same as that one used for import/export by PCB Editor.

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Support for page-level team design with Allegro Design Authoring Team Design Option
A significant advancement in Allegro design management features is the ability to manage designs at the page level, for both hierarchical and flat designs.

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Graphical Design Difference Viewer in Allegro Design Entry Capture
Graphical Design Difference Viewer is a powerful, real-time, design difference, visual review utility in Allegro Design Entry Capture with the ability to perform logical as well as graphical comparisons on a page-by-page basis.

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Advanced Annotation in Allegro Design Entry Capture
With the newly introduced Advanced Annotation feature supported by Allegro Design Entry Capture, users can assign reference ranges hierarchically by automatically assigning values and perform annotation on the whole design, on hierarchy block at any level.

PSpice virtual prototyping in Allegro AMS Simulator
New functionality introduced in PSpice® helps to overcome design challenges for electrical engineers by automating the code generation for multilevel abstraction models written in C/C++, SystemC.

New pin assignment options in FPGA System Planner
A new “FSP Bundle Swap” option is available. If the two bundles are the same size, the PCB designer can select the bundles and ask the FPGA System Planner engine to swap them, pin for pin. FPGA System Planner 17.2 also offers three new manual pin-swapping algorithms: show all destination pins, show all destination pins in the same bank, and two-pin selection.

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Create custom connectors with user-defined groups and pin types in FPGA System Planner
Users can now create complex connector models with user-defined pin types and signal group capabilities.

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Optimize multiple, separate FPGA System Planner designs in Allegro PCB Editor
When selecting the FPGA System Planner project in Allegro PCB Editor, the PCB designer can select any one of several FPGA System Planner projects that are part of the master design.

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Other enhancements
  • New “Targeted Pin View” option in the Design Connectivity window
  • Enhanced net name template
  • Instance-level targeted pin function override
  • Hyperlinked error messages when checking protocols, rules, and virtual interfaces
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New Allegro EDM Capabilities

Team design capability integrated into Allegro DE-HDL
All of the team design functionality is now built directly into Allegro Design Authoring DE-HDL. Team members can stay within DE-HDL to check out/in designs using menus integrated into the DE-HDL hierarchy viewer or by using a design dashboard. And users have the ability to manage designs at the page level, for both hierarchical and flat designs.

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Hierarchical split symbol support
Hierarchical split symbols can now be managed with Allegro Library Manager.

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Support for managing the “standard” library
Allegro EDM 17.2 now supports the standard library that contains the page borders, ioports, taps, power symbols, etc., so that librarians can not only manage these parts, engineers can stay connected to the database to select them.

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The Cadence® Allegro® 16.6 release has continually provided improvements and updates through Quarterly Incremental Releases. The latest release, Allegro 16.6-2015, includes new improvements and products to help printed circuit board (PCB) designers achieve maximum efficiency and productivity while keeping ownership costs low.

New Allegro Products:

Allegro PCB Designer Manufacturing Option
The Allegro PCB Designer Manufacturing Option is a comprehensive, powerful, easy-to-use suite of tools that makes it efficient for PCB designers to streamline the development of release-to-manufacturing packages for their products. It includes three modules: Design for Manufacturing (DFM) Checker, Documentation Editor, and Panel Editor.

Figure 1. DFM Checker - Use of hierarchical rule sets helps identify defects, avoiding costly bare board scrap
DFM Checker
Allegro PCB Designer Manufacturing Option’s DFM Checker module is a suite of manufacturing analysis tools that helps engineers and designers ensure no fabrication-related issues are present before sending the design off for fabrication, thereby helping to avoiding fabrication-related delays, additional costs, and re-work.
Figure 2. Documentation Editor - Produce complex PCB documentation in a fraction of the time
Documentation Editor
Allegro PCB Designer Manufacturing Option’s Documentation Editor module is a PCB documentation-authoring tool that intelligently automates your documentation creation process to produce complex PCB documentation in a fraction of the time versus traditional methods. Documentation Editor enables you to quickly create the manufacturing drawings that drive PCB fabrication and assembly.
Figure 3. Panel Editor - Use the existing PCB and NC milling data to automatically depict mill tab and V-score details
Panel Editor
Allegro PCB Designer Manufacturing Option’s Panel Editor module intelligently automates the complex process of panel definition and documentation, simplifying the design process. This solution enables designers to quickly create electronic manufacturing documents that clearly articulate the panel specification and instructions for successful fabrication, assembly, and inspection of their designs.
Allegro Rules Developer and Checker
Allegro Rules Developer and Checker allows you to develop custom fabrication and assembly rules to extend capabilities provided by Allegro PCB Designer and the Manufacturing Option. This tool provides a relational geometric verification language designed specifically for creating rules that are proprietary and custom to an original equipment manufacturer (OEM). The rules can be viewed and executed from the Allegro Constraint Manager, making it a single source for all design rules checks (DRCs) within a PCB.
New Allegro 16.6-2015 Release Capabilities
Major feature updates include:
  • New shape editing environment as a dedicated application mode focused on improving boundary editing. Context menu or single-pick execution mode command access for slide edges with corners, chamfer/round corners, join edges, add notches, and multi-segment movement
    Figure 4. ShapeApp mode makes it easy for users to edit complex shapes quickly
  • Ability to add ground current return path vias to differential pairs during Add Connect. User can select from one of many configurations supported with parameters.
    Figure 5. Ground current return path via structures available for differential pairs during AddConnect
  • Adjust spacing: During route engine-assisted auto-connect routing, users can compress spreading of traces in the trunk of a set of signals. It will also nudge/push existing traces.
    Figure 6: User selects a set of signals, route engine creates flow automatically: create flow followed by auto connect with compression
  • Snake routing improvements for fine-pitch BGAs allow users to route quickly, easily, and with ability to restart from a previously routed path
    Figure 7: Snake routing
  • Off-angle routing
    • Users can now very quickly create off-angle routes to avoid FR4 fiber weave coupling and achieve better impedance control
      Figure 8: Fabric weave zig-zag routing
    • Auto-interactive Phase Tuning (AiPT) now supports bumps on off-angle routes
  • Improved arc support in routing
    • Improved support for push-n-shove with arcs
    • AiPT arcs on tuning bumps
    • Auto-interactive Delay Tuning (AiDT) supports arcs on tuning bumps
The following capabilities are now available in Allegro PCB Designer (base):
  • Extended net (Xnet) creation
  • Differential-pair dynamic phase control
  • Detecting segment over voids for possible return path problems
  • Spread lines between anti-pads to manage return path issues particularly under fine-pitch BGAs
  • Hug contour routing on flexible PCBs
  • Line fattening
  • Signal Explorer for topology design and control
Approved Manufacturer List (AML) support in ADW library and component browser

Brings component manufacturer data, which is often in a different corporate database, into the ADW library to supplement existing internal part numbers

Provides additional searchable information to design engineers’ desktops

Reduces time to research and choose parts

AML data imported from corporate PLM, MRP/ERP systems
Allegro 16.6 Quarterly Incremental Report »

The Cadence Allegro 16.6 release offers numerous new features and enhancements that make it easy to design PCBs, from the simplest to the most complex. Now users can collaborate across geographically dispersed teams through an efficient design collaboration environment that leverages Microsoft SharePoint 2010. Additional highlights include FPGA “Planning Mode” (auto-interactive pin-reassignment) inside PCB Editor using Allegro FPGA System Planner under-the-hood, and auto-interactive route delay tuning to accelerate timing closure on critical high-speed signals by 30-50%.

Cadence Allegro and OrCAD 16.5 provides customers with new capabilities for a shorter, predictable, and convergent path to product creation. The latest Allegro technology is now available through flexible on-demand product configurations that offer cost-efficiency and scalability. Allegro 16.5 spans silicon, SoC, and system-level development and offers PCB designers benefits such as:
  • Higher functional density with a constraint-driven flow for embedded components
  • Faster timing closure with new PCB interconnect design planning technology
  • Fewer physical prototype iterations with concurrent team design authoring
  • More efficient low-power design with integrated power delivery network analysis
  • A compliant and faster implementation path with package/board-aware SoC IP
  • Smoother collaboration among global teams with new SiP distributed co-design
  • Flexibility through “base plus options” configurations
OrCAD is now more powerful with 3 new PCB configurations: OrCAD Designer Professional, OrCAD Designer Standard and OrCAD Designer Lite that provide the lowest cost of ownership ever.

Each Allegro product area has a “What’s New” tab that provides details on what is “new” for this latest release
Hierarchical Interface-Level Design Across Design Authoring, Constraints, and Layout
Defines and constrains interfaces.

Accelerates design intent authoring with interfaces.

Guides and plans placement using interfaces.

Accelerates routing and timing closure using interfaces with innovative auto-interactive technologies.

Auto-Interactive Interface Trunk Routing, Scribble Routing
Route to trunk for interfaces
Used in conjunction with breakout planning to route main body (trunk) of an interface.



Split view
Initially introduced with Auto-interactive Breakout tuning, users can use split views to see one end of an interface bundle in one view and the other end of the interface in another allowing users to zoom into the two ends.



Scribble routing
Scribble is a simple routing mode that allows you to ‘scribble’ a route path onto the canvas. Once a click is made, the etch solution for the scribble path will be generated. Scribble provides a quick two-pick methodology to generate complex route paths, along with very controlled usage of push/shove based on the scribble path.

Slide Etch During Component Move
Auto re-routes etch to either 45 or 90 degree angles, eliminating time to clean up etch after moving a component that is already routed.



IPC2581 Manufacturing Output Supports Latest RevB Specification
IPC2581 provides an intelligent, robust methodology for driving manufacturing. Allegro PCB Editor has supported IPC-2581 since 16.5 release. This QIR allows users to output IPC-2581 in RevB format and supports enhancements for assembly data (Pin1, Polarity markings, pick up point, and other assembly-related data). For more information about IPC-2581 consortium, visit www.ipc2581.com.

PADS PowerPCB Footprint Library Translation
Allows users to translate PADS PowerPCB footprint library to Allegro® Footprints.

ADW Integration with PTC Windchill for Component Data and Team Design Data Management
Compatible with WC 10.2 M010 release in December 2013.

Provides work-in-progress design data management for PCB designs.

Dynamic Rat Suppression
All rats expect active net are temporarily suppressed during Add Connect.

De-clutters canvas during routing improving designer productivity.

New Drafting Capabilities
Relative move and copy: move and copy elements about a user-specified axis.

Drafting functions introduced in previous QIRs:
  • Add parallel line
  • Add perpendicular line
  • Delete by line
  • Delete by rectangle
  • Offset copy
  • Offset move
  • Relative copy
  • Relative move
Allegro PCB Analog/RF Option Integrates with AWR’s MWO
Support for Microwave Office (MWO) stripline and microstripline library components.

Import schematics from MWO into Allegro Design Authoring (DE-HDL).

Import and export of RF design from MWO to Allegro PCB Analog/RF Option.