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PCB Design 

Bayside Design Inc
Design Challenge
Develop a complete evaluation system for 6.5-Gbps SerDes design, including package, board, FPGA, and software for debug
Complete project in eight weeks

Cadence Solution
Upgraded design environment with Cadence Allegro® system interconnect design platform
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Cavium
Challenges
  • Address increasing schedule pressures for complex, high-speed evaluation boards
  • Accelerate timing closure process while maintaining high quality of boards
  • Take on more projects with current staffing level
Cadence Solutions
  • Allegro® TimingVision™ environment
  • Allegro PCB Designer
  • Allegro PCB Router (previously known as SPECCTRA®)
Lessons Learned
  • Route DDR4 signals spaced at 5X the line width for better noise/coupling immunity
  • Ensure that differential pairs (static and dynamic phases) are all matched before trying to match lengths for all signals in a byte lane
  • Use application modes within Allegro PCB Designer to further increase tuning efficiency
  • Take advantage of user-redefinable, application-mode-sensitive “funckeys” to further shorten overall tuning proces
Results
  • 4X faster timing closure, without compromise on quality
  • Ability to take on increased volume of PCB designs with existing resources
  • Faster “what-if” analysis with fewer layers for boards for routing DDRx interfaces
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Huawei Technologies
Design Challenge
Create a next-generation basestation that incorporates extensive new technologies and significant mixed-signal design challenges
Reduce design cycle and improve productivity

Cadence Solution
Provided custom radio frequency (RF) printed circuit board (PCB) module for Cadence Allegro® system interconnect design platform
Created an environment that allowed Huawei to complete their entire PCB design within the Allegro platform
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IBM
Design Challenge
World's most complex PCBs
Large designs, multiple wide buses
High component pin counts and thousands of board connections

Cadence Solution
Integrated platform—from input to final design
Tabular input of signal information for faster compilations
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IN2P3
Business Challenge
  • Enhance ability to meet aggressive deadlines for particle physics research projects
Design Challenges
  • Automate aspects of FPGA board design, including pin placement and routing schemes
  • Quickly select the optimal FPGA package and pin count for the design
  • Quickly determine the right FPGA configuration and component setup for the design
Cadence Solutions
  • Allegro FPGA System Planner
  • Allegro Design Authoring
  • Allegro PCB Designer
  • Allegro PCB SI
Results
  • Saved one to two months based on FPGA interconnect density on manual FPGA design-in effort for initial design
  • Made late changes to the design easily and in hours vs. weeks
  • Reduced design iterations and, as a result, costs
  • Saved one month of project time due to co-design development ability
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JDSU
Design Challenge
Pin assignment for multiple FPGAs on a new optical network tester board
High-density, multi-port design with 5,500 components and stringent communications requirements
4,596 high-speed nets with constraints

Cadence Solution
Cadence Allegro FPGA System Planner
Cadence Allegro Global Route Environment
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Liquid Computing Corporation
Design Challenge
Accelerate design schedule for complex high-speed board design to meet critical market window
Adopt an front-to-back high-speed board design methodology to maximize productivity

Cadence Solution
Deployed the Cadence® Allegro® system interconnect design platform
Enabled a high-speed board design methodology that allowed the Liquid Computing team to accelerate their process to meet their schedule
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Marconi Communications
Design Challenge
Migrate to a new PCB design environment with advanced board design methodologies
Translate INCASES libraries to new platform

Cadence Solution
Provided complete assessment and translation of EDA library infrastructure
Trained team on new platform
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NVIDIA
Design Challenge
Having HDI design capabilities in a constraint-driven PCB design flow
Driving micro vias quickly and accurately
Reducing the number of layers on customers’ boards
Shortening the PCB layout design cycle

Cadence Solution
High-speed constraint-driven HDI flow to shorten the design cycle while adhering to high-speed rules
Mitigate risk, boost performance, and increase efficiency with a set of proven, unified PCB design, layout, editing, and routing technologies
Collaboration with NVIDIA engineers to streamline time to productivity with the enhanced flow
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Nvidia
Greg Bodi
Nvidia

Greg Bodi, System Design Senior Manger at Nvidia talks about Allegro PCB products.

Pegatron
Business Challenges
  • Free up resources to support more project requests
  • Enhance productivity of layout team
Design Challenge
  • Faster routing and tuning process for boards
Cadence Solutions
  • Allegro PCB Designer (Auto Interaction Delay Tune feature)
  • Full Allegro suite of products
  • Full OrCAD suite of products
Results
  • Up to 67% faster routing process
  • 75% reduction in engineering resources required for routing and tuning, freeing engineers to work on new projects
  • Faster tuning time
  • Increased customer satisfaction
  • Decrease in errors due to 300 utilities developed in Allegro PCB Designer
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Polycom
Business Challenges
  • Automate PCB design routing for faster time to market
  • Continually enhance quality of PCB designs
  • Identify more detailed design constraints
Cadence Solutions
  • Allegro PCB Router
  • Allegro PCB Designer
  • OrCAD Capture CIS
Lessons Learned
  • Spend more upfront time capturing design intent
  • Have design constraints in place before placing the board
Results
  • 10% faster time to market for boards, with 25% faster PCB design cycle
  • $50K saved annually through greater layout design efficiencies, which eliminates need to hire outside layout staff during busy cycles
  • Ability to perform “what if” analysis, resulting in better quality boards
  • Achieving higher quality avoids the tens of thousands of dollars that could be spent in the event of a respin
  • Better alignment between industrial and mechanical design phases contributes to better product quality
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Tait Electronics
Design Challenge
Translate legacy UniCAD designs to Cadence Concept® HDL and Allegro® formats
Reduce design cycle time

Cadence Solution
Customized translators and converted libraries from UniCAD to Cadence
Customized Cadence Allegro platform to meet customer design needs
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VeriSilicon
Design Challenges
Accelerate the design process with automated, placement-aware pin assignment
Optimize the physical connectivity, even as it changes
Ensure quality and reduce complexity with reuse of interface rules and protocols

Cadence Solution
Allegro FPGA System Planner XL
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Dialog Semiconductor
Rajesh Aiyandra
Dialog Semiconductor

Dialog Semiconductor faced a potentially daunting challenge: reduce the size and cost of its PCBs via embedded passive devices at the substrate level. The company needed a tool that could help migrate from a two-layer BGA substrate to four layers. Rajesh Aiyandra, package design and simulation team leader at Dialog, explains how Cadence SiP Digital Layout helped deliver a smooth migration, from the change in the number of layers to the change in the via specifications.

EDAis
Yael Arbel
EDAis

EDAis, a Cadence® Channel Partner, is the biggest EDA tools distributor in Israel serving over 600 customers in industries including military, medical, and automotive. In this 2-minute video, Yael Arbel, who is responsible for selling Cadence OrCAD® PCB design tools, talks about meeting the needs of a very challenging, fast-moving market and why the OrCAD PCB design tools are the most popular in Israel.

Ericsson
Sheetal Jain
Ericsson

In this video from CDNLive India 2014, Sheetal Jain, a member of the modem organization at Ericsson Design, discusses how his team verified their design to meet DDR and PCIe specs while avoiding crosstalk. They were able to simulate and verify using Cadence's Sigrity™ solution with the IBIS/AMI virtual reference design for interface compliance signoff, which they found to be easy to set up and easy to test, while saving them time and money.

Faraday Technology
Business Challenge
  • Produce prototype of highly complex, 300-million-gate SoC—the 1st such effort in Taiwan—in 7 months
  • Grow business through ability to develop large-scale chip designs
Design Challenges
  • Shorten verification and analyses processes
  • Process large database for huge SoC design
  • Manage and integrate different technologies across industries
Cadence Solutions
  • First Encounter® Design Exploration and Prototyping
  • Encounter® Digital Implementation System
  • Encounter Conformal® Equivalence Checker
  • Incisive® verification platform
  • Sigrity™ packaging and PCB signal and power analysis solutions
  • Verification IP Catalog
Results
  • Completed complex design from data-in to tapeout within 7 months
  • Reduced one iteration for timing optimization, extraction, analysis and verification of physical design down to 4 days
  • Expanded design capacity by 10X
 Read full story»

FTD Automation
Mahendra
FTD Automation

FTD Automation is a Cadence® channel partner in India. In this video, Mahendra, a Sr. applications engineer at FTD Automation, talks about the time-to-market and scalability benefits of Cadence OrCAD® PCB design tools. These tools, says, Mahendra, help design engineers address challenges including design complexity and cost, with capabilities including fully integrated schematic entry, signal integrity analysis, and place-and-route methodology.

Hyundai MOBIS
Imran Shaik
Hyundai MOBIS

Automotive parts manufacturer Hyundai MOBIS was facing electromagnetic interference (EMI) problems with its PCB designs. In this short video clip, Imran Shaik, a project lead on EMI simulations, discusses how Cadence® Sigrity™ PowerSI™ and Cadence Sigrity SPEED2000™ helped the company reduce its PCB testing time and get its products to market faster.

Lattice
Maryam Shahbazi
Lattice

Lattice is a global leader in delivering ultra-low power FPGAs for manufacturers of smartphones, small cell networking equipment, and industrial applications. For its customer base, fast time to market, low power, and low cost are important considerations. In this video, Maryam Shahbazi of Lattice's Systems Development Group talks about how the company relies on Cadence® Sigrity™ tools to model its power delivery network, solve power integrity issues, and improve voltage margins.

Nexus Technology
Joe Socha
Nexus Technology

At Nexus Technology, Joe Socha, signal integrity engineer, is responsible for analyzing tiny PCBs that are used as interposers between memory devices and their target systems. Probing memory devices can be difficult, but an interposer allows the engineer to gain signal access. In devices such as DDR4 and LPDDR4, there are electrical and mechanical challenges that Nexus manages by using Cadence® Allegro® and Sigrity™ tools. In this video, Socha talks about how the Cadence Sigrity PowerSI® tool enables the team to run what-if cases to gain insights that lead to useful changes in trace widths, impedance, and more.

Open-Silicon, Inc.
Kavitha Nagarajan
Open-Silicon, Inc.

Kavitha Nagarajan, Lead Engineer – IC Package Design at Open-Silicon, Inc., describes how the company leveraged the Cadence Integrated SPB environment to successfully complete a complex project with a tight deadline.