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Allegro FPGA System Planner 


FPGA rules driven FPGA-PCB co-design

The Cadence® Allegro® FPGA System Planner offers a complete, scalable technology for FPGA-PCB co-design that allows users to create an optimum correct-by-construction pin assignment. FPGA pin assignment is synthesized automatically based on user-specified, interface-based connectivity, FPGA device pin assignment rules, and placement of FPGAs on the PCB. With automatic pin assignment synthesis, users avoid manual error-prone processes while shortening the time to create initial pin assignment that accounts for FPGA placement on the PCB. This unique placement-aware pin assignment approach eliminates unnecessary physical design iterations that are inherent in manual approaches while shortening the design cycle time.

ASIC Prototyping Simplified Technical Paper »
Allegro FPGA System Planner Datasheet »



Cadence/Xilinx webinar: Accelerating design-in of Xilinx FPGAs while optimizing PCB layout for cost and performance »
Cadence/Altera webinar: Accelerating FPGA Design-in and optimizing PCB layout »

Allegro FPGA System Planner (16.6 release)
  • Support for additional FPGA architectures from Actel (ProASIC3), Altera (Cyclone V, Stratix V), and Xilinx (Virtex 7)
  • Auto-interactive pin-swap (“Planning Mode”) for FPGAs within Allegro PCB Editor using Allegro FPGA System Planner under-the-hood
  • Support for new termination schemes
    • Power filters and terminators are separate objects
    • Terminators are added to schematic sheets (no hierarchy needed)
    • Reuse placement from an existing board (design reuse)