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Allegro FPGA System Planner 


FPGA rules driven FPGA-PCB co-design

The Cadence® Allegro® FPGA System Planner offers a complete, scalable technology for FPGA-PCB co-design that allows users to create an optimum correct-by-construction pin assignment. FPGA pin assignment is synthesized automatically based on user-specified, interface-based connectivity, FPGA device pin assignment rules, and placement of FPGAs on the PCB. With automatic pin assignment synthesis, users avoid manual error-prone processes while shortening the time to create initial pin assignment that accounts for FPGA placement on the PCB. This unique placement-aware pin assignment approach eliminates unnecessary physical design iterations that are inherent in manual approaches while shortening the design cycle time.

ASIC Prototyping Simplified Technical Paper »
Allegro FPGA System Planner Datasheet »



Cadence/Xilinx webinar: Accelerating design-in of Xilinx FPGAs while optimizing PCB layout for cost and performance »
Cadence/Altera webinar: Accelerating FPGA Design-in and optimizing PCB layout »

Product ImageBy enabling placement-aware pin assignment synthesis—which is FPGA device rules accurate—the Allegro FPGA System Planner offers a unique set of capabilities for FPGA-PCB co-design. It provides a floorplan view to place components in the FPGA system and allows users to specify connectivity between components within the FPGA sub-system at a higher level through interface definitions. With its placement aware-pin assignment synthesis, the Allegro FPGA System Planner enables users to explore their FPGA-based architecture and to create an optimum correct-by-construction pin assignment for either production or prototype designs that use FPGAs.

Features/Benefits
  • Scalable FPGA-PCB co-design solution from OrCAD Capture to Allegro GXL
  • Shortens time for optimum initial pin assignment, accelerating PCB design schedules
  • Accelerates integration of FPGAs with Cadence PCB design creation environments
  • Eliminates unnecessary, frustrating design iterations during the PCB layout process
  • Eliminates unnecessary physical prototype iterations due to FPGA pin assignment errors
  • Reduces PCB layer count through placement-aware pin assignment and optimization
  • Enables interface-based connectivity definition for the FPGA system
  • Enables placement-aware pin assignment synthesis that is FPGA-DRC accurate
  • Allows architectural exploration for FPGA system
  • Speeds ASIC prototyping using FPGAs