16.6 Release 16.5 Release
Allegro 16.6 Quarterly Incremental Report »
The Cadence Allegro 16.6 release offers numerous new features and enhancements that make it easy to design PCBs, from the simplest to the most complex. Now users can collaborate across geographically dispersed teams through an efficient design collaboration environment that leverages Microsoft SharePoint 2010. Additional highlights include FPGA “Planning Mode” (auto-interactive pin-reassignment) inside PCB Editor using Allegro FPGA System Planner under-the-hood, and auto-interactive route delay tuning to accelerate timing closure on critical high-speed signals by 30-50%.
Cadence Allegro and OrCAD 16.5 provides customers with new capabilities for a shorter, predictable, and convergent path to product creation. The latest Allegro technology is now available through flexible on-demand product configurations that offer cost-efficiency and scalability. Allegro 16.5 spans silicon, SoC, and system-level development and offers PCB designers benefits such as:
- Higher functional density with a constraint-driven flow for embedded components
- Faster timing closure with new PCB interconnect design planning technology
- Fewer physical prototype iterations with concurrent team design authoring
- More efficient low-power design with integrated power delivery network analysis
- A compliant and faster implementation path with package/board-aware SoC IP
- Smoother collaboration among global teams with new SiP distributed co-design
- Flexibility through “base plus options” configurations
OrCAD is now more powerful with 3 new PCB configurations: OrCAD Designer Professional, OrCAD Designer Standard and OrCAD Designer Lite that provide the lowest cost of ownership ever.
Each Allegro product area has a “What’s New” tab that provides details on what is “new” for this latest release