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In release 16.0, the concept of Application Modes was introduced. These application modes are used to set up the tool for specific tasks. The existing applications are General Edit, Etch Edit, and Placement. In 16.5, the Signal Integrity (SI) application mode has been added to be used for high-speed related tasks. An Application Mode is a &ldq... Read more » In System in Package (SiP) 16.3, the co-design die flow introduced the distributed co-design flow concept, where there is no direct interaction with I/O Planner. Die information flowing between Encounter and SiP Layout is done via a die abstract. In flows up through 16.3, you first need to load the LEF files for the cell library used by the... Read more » The 16.5 Global Route Environment ( GRE ) now allows or prohibits tuning in constraint regions. This functionality was designed to help PCB designers prevent delay routing in constraint regions. This is generally desirable as the space is so tight in the BGA via field that there is little room and what little there is -- is needed for routing. I... Read more »
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