Cadence Design Systems, Inc.
Home
|
Worldwide
|
Contact us
PRODUCTS
Cadence Kits
Incisive functional verification
Encounter digital IC design
Virtuoso custom design
Allegro IC-PKG-PCB co-design
OrCAD PCB design
System-in-package design
Design for manufacturing
IP catalog
|
SOLUTIONS
Advanced node design
Low power
Logic design
Advanced verification
Digital implementation
Custom design
PCB design
Advanced packaging
|
SUPPORT
Support process
SourceLink
Software downloads
Education
University software programs
User community
Computing platform support
|
SERVICES
Incisive functional verification
Encounter digital IC design
Virtuoso custom IC design
Allegro IC-PKG-PCB co-design
PCI Express vertical solution
Ethernet vertical solution
Low-power design services
PowerPC design services
Silicon engineering
European start-up accelerator
Working with us
|
ALLIANCES
Verification Alliance program
Power Forward Initiative
Foundry program
OpenChoice program
Connections program
Channel partner program
ASIC program
Standards and languages
Industry memberships
|
COMPANY
Executive team
Executive Briefing Center
Newsroom
Events and webinars
Investor relations
Success stories
Cadence labs
Employment
Community involvement
Cadence advertising gallery
Logos
PRODUCTS
OrCAD Capture
OrCAD PCB Designer
OrCAD Signal Explorer
PSpice simulation
DESIGN CREATION
Design creation
Simulation
PCB layout and routing
PCB signal integrity
Library and design data management
Products A-Z
-Acceleration/emulation
-Allegro AMS Simulator
-Allegro Design Entry CIS
-Allegro Design Entry HDL
-Allegro Design Publisher
-Allegro Design Workbench
-Allegro Package Designer
-Allegro Package SI
-Allegro PCB Design
-Allegro PCB Librarian
-Allegro PCB SI
-Allegro System Architect
-Analog-mixed signal
-Assura DRC
-Assura LVS
-Assura RCX
-Cadence 3D Design Viewer
-Cadence and
Agilent technologies RF IC partnership
-Cadence Chip Optimizer
-Cadence CMP Predictor
-Cadence Litho
Electrical Analyzer
-Cadence Litho Physical Analyzer
-Cadence MaskCompose Suite
-Cadence QRC Extraction
-Cadence SiP Digital Architect
-Cadence SiP Digital Layout
-Cadence SiP Digital SI
-Cadence SiP RF Architect
-Cadence SiP RF Layout
-Cadence Space-Based Router
-CeltIC NDC
-Diva Physical Verification
-Dracula
-Encounter Conformal
Constraint Designer
-Encounter Conformal ECO Designer
-Encounter Conformal
Equivalence Checker
-Encounter Conformal Low Power
-Encounter Library Characterizer
-Encounter RTL Compiler
-Encounter Test
-Encounter Timing System
-Fire & Ice QX
-First Encounter
-Formal analysis
-Incisive Acceleration
and Emulation
-Incisive Design Team family
-Incisive Enterprise family
-Incisive HDL family
-Incisive Unified Simulator
-Incisive XLD
-Incisive XLD Base
-NanoRoute
-NC-SC
-NC-Verilog
-NC-VHDL
-OrCAD Capture
-OrCAD PCB Designer
-OrCAD Signal Explorer
-Other Virtuoso Products
-Palladium series
-Physical Verification System
-Plan-to-Closure Methodology
-PSpice simulation
-Simulation
-SoC Encounter
-Testbench automation
-Verification IP
-Verification management
-Virtuoso AMS Designer Simulator
-Virtuoso Analog
ElectronStorm Option
-Virtuoso Analog
VoltageStorm Option
-Virtuoso Chip Editor
-Virtuoso Digital Implementation
-Virtuoso Layout Migrate
-Virtuoso Multi-Mode Simulation
-Virtuoso Passive
Component Designer
-Virtuoso platform GXL
-Virtuoso platform L
-Virtuoso platform XL
-Virtuoso RET Suite
-Virtuoso RF Designer
-Virtuoso Spectre
Circuit Simulator
-Virtuoso Spectre
RF Simulation Option
-Virtuoso UltraSim
Full-chip Simulator
-VoltageStorm
-Xtreme series
Home
>
Products
>
OrCAD PCB design
>
OrCAD PCB design Application Notes
OrCAD PCB design application notes
Transmission Line Applications in PSpice
SPICE Modeling Convergence Explored
Obtain S-Parameter Data Obtain S-Parameter Data from Probe
Creating a Digital I/O Model for an Inverter for PSpice
Modeling Voltage-Controlled and Temperature Dependent Resistors
Modeling Photodiodes, LEDs and Laser Diodes
A Nonlinear Capacitor Model for Use in PSpice
Analog Behavioral Modeling
Analyzing Amplifier's Settling Time Using Performance Analysis
Using Constrained Optimization to Improve Circuit Performance
Creating Discrete Values Tables for Advanced Analysis Optimizer
Creating "Eye" Displays Using Probe in PSpice
Using Ferrite Bead Models to Analyze EMI Suppression
Importing Legacy PSpice Optimizer Projects
PSpice Advanced Analysis: Interpreting Bar Graph Results in Sensitivity Analysis
Modeling a High-speed Digital Bus with PSpice
Modeling Metal Oxide Varistors
Modeling Non-linear Inductors
Simulating Power Circuits
Specifying Advanced Analysis Monte Carlo Distribution Functions
Using Coupled Inductors and Inductor Cores
Using Multipliers for Signal Processing
What Will Digital Worst-Case Timing Simulation Do For You?
