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Voltus IC Power Integrity Solution 

Advanced technologies for fastest power signoff and design closure

Cadence® Voltus™ IC Power Integrity Solution is a full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies to designers for debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration (EM) constraints and violations. The solution includes innovative technologies such as massively parallel execution, hierarchical architecture, and physically aware power grid analysis and optimization. Beneficial as a standalone power signoff tool, Voltus IC Power Integrity Solution delivers even more significant productivity gains when used in a highly integrated flow with other key Cadence products, providing the industry’s fastest design closure technology. When used with Voltus-Fi Custom Power Integrity Solution, a transistor-level electromigration and IR-drop (EMIR) tool delivering foundry-certified SPICE-level accuracy, the resulting platform accelerates IC power signoff and overall design closure.

Power integrity no longer has to be a design signoff bottleneck. Voltus IC Power Integrity Solution equips you to complete power analysis up to 10X faster than with competing solutions. Use the product to:
  • Calculate and analyze power consumption
  • Analyze and optimize EMIR
  • Analyze impact of power on design closure, from chip to package to PCB
Developed with advanced algorithms and a power integrity analysis engine with massively parallel execution, the solution:
  • Delivers power signoff accuracy via advanced algorithms in a SPICE-level matrix solver, accurate signoff-quality power grid RC extraction, and accurate instance power distribution
  • Supports designs with up to one billion instances with its hierarchical architecture
  • Enhances physical implementation quality via physically aware power integrity optimization
  • Provides early rail analysis at floorplanning and power planning to foster correct-by-construction power grid design and remove correlation risks between implementation and signoff
  • Provides automatic de-coupling capacitance analysis and optimization, as well as automatic power-gating analysis and optimization
Supported by major foundries and intellectual property (IP) providers, Voltus IC Power Integrity Solution has been validated and certified on advanced node processes such as 16nm FinFET and included in reference design flows such as for 3D-IC technology.

Fastest Design Closure Flow
When you use Voltus IC Power Integrity Solution with Voltus-Fi Custom Power Integrity Solution, both tightly integrated with several other Cadence tools, you’ll have the industry’s fastest design closure flow.
  • Get a unified electrical signoff flow with Cadence Tempus™ Timing Signoff Solution and Quantus™ QRC Extraction Solution
  • Bring power grid design to the early stage of physical implementation with an early rail analysis capability via the Cadence Encounter® Digital Implementation System
  • Get accurate IC power integrity analysis, driven by real-world power simulation vectors, with Cadence Palladium® technology
  • Benefit from chip-package-PCB co-simulation and analysis with Cadence Allegro® Sigrity® technology
Key Features and Benefits
  • Automatic de-coupling capacitance analysis and optimization, including cell swapping, cell removal and engineering change order (ECO) flow for physical implementation
  • Automatic power gating analysis and optimization, including steady states, power ramp-up, and ECO flow for physical implementation
  • Co-simulation flow linked to Cadence Spectre® Accelerated Parallel Simulator (APS) for analysis of the on-chip LDO voltage regulator and its impact on IR drop and EM
  • Power GUI for an easy-to-use debugging environment, including instance-based effective-resistance analysis with automatic least-resistive path highlighting


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