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Voltus IC Power Integrity Solution 


Advanced technologies for fastest power signoff and design closure

Cadence® Voltus™ IC Power Integrity Solution is a full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies to designers for debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration (EM) constraints and violations. The Voltus solution includes innovative technologies such as massively parallel execution, hierarchical architecture, and physically aware power grid analysis and optimization. Beneficial as a standalone power signoff tool, Voltus IC Power Integrity Solution delivers even more significant productivity gains when used in a highly integrated flow with other key Cadence products, providing the industry’s fastest design closure technology.
Built on production-proven, signoff-quality algorithms, Voltus IC Power Integrity Solution primarily performs vectorless or vector-based static and dynamic IR drop and EM analysis and optimization, including power integrity impacts due to advanced design techniques such as power gating switches and on-chip LDO voltage regulators. As an integral, and critical, piece of a comprehensive power integrity eco-system consisting of Cadence products, the Voltus solution brings its signoff-quality power technology throughout the entire IC and system design implementation stages. As such, the tool’s reach spans from floorplanning’s power grid estimation to unified electrical design signoff in power and timing to the chip assembly phase’s chip-package-PCB co-simulation. This highly integrated flow also greatly reduces a product’s overall time-to-market window, since it removes the excessive design iterations that a point tool solution leads to.

Supported by major foundries and intellectual property (IP) providers, Voltus IC Power Integrity Solution has been validated and certified on advanced nodes processes such as 16nm FinFET and included in reference design flows such as for 3D-IC technology. Backed by Cadence’s rigorous quality control and product release procedures, the Voltus solution delivers best-in-class signoff quality on accuracy and stability for all process nodes and design technologies.

Key Features and Benefits
  • Power signoff accuracy via advanced algorithms in SPICE-level matrix solver, accurate signoff-quality power grid RC extraction, and accurate instance power distribution
  • High performance with multi-CPU scalability via distributed, multi-threaded massively parallel execution
  • High-capacity support for up to one billion instances via hierarchical architecture and parallel execution
  • Unified electrical signoff solution for faster timing and power convergence through its integration with Cadence Tempus™ Timing Signoff Solution
  • Early rail analysis (ERA) at floorplanning and power planning stages allows correct-by-construction power grid design and removes correlation risks between implementation and signoff
  • Automatic de-coupling capacitance analysis and optimization, including cell swapping, cell removal and engineering change order (ECO) flow for physical implementation
  • Automatic power gating analysis and optimization, including steady states, power ramp-up, and ECO flow for physical implementation
  • Co-simulation flow linked to Cadence Spectre® Accelerated Parallel Simulator (APS) for analysis of the on-chip LDO voltage regulator and its impact on IR drop and EM
  • Power GUI for an easy-to-use debugging environment, including instance-based effective-resistance analysis with automatic least-resistive path highlighting
  • Integration with other key Cadence products, delivering the industry’s fastest path to design closure and signoff
    • Encounter® Digital Implementation System: physically aware power grid optimization through automatic ECO flows
    • Allegro® Sigrity® Power Integrity: a comprehensive, co-simulation based power integrity solution spanning from chip to package to PCB
    • Virtuoso® platform: analysis of analog/custom IP in an analog/mixed-signal SoC design
    • Palladium® Dynamic Power Analysis: real-world, application-specific power simulation vectors from Palladium platform’s Dynamic Power Analysis (DPA) feature drive the Voltus solution’s vector and power density profiling for the most accurate vector-based power integrity analysis

 

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