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Voltus-Fi Custom Power Integrity Solution 


Transistor-level EMIR tool with SPICE-level accuracy

Cadence now offers a complete platform that accelerates IC power signoff and overall design closure. The Voltus™-Fi Custom Power Integrity Solution is a transistor-level electromigration and IR-drop (EMIR) tool that delivers foundry-certified SPICE-level accuracy in power signoff. The Voltus IC Power Integrity Solution is a full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies for debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration constraints and violations. These complementary solutions are part of an integrated flow featuring the electronics industry’s fastest design closure technologies.

EMIR presents unique challenges at the transistor level, from complex EM rules to the high costs of simulating for current on a large RC network from post-layout. Enabled by Cadence Spectre® Accelerated Parallel Simulator signoff SPICE simulation, Voltus-Fi Custom Power Integrity Solution shortens power signoff closure and analysis through:
  • Our patented voltage-based iteration method, which calls for a smaller memory footprint and runs faster than the industry’s traditional current-based iteration method. In the first stage, a RC reduced simulation is run to collect the voltage profile at tap device points. Then, the collected profile is applied to the entire RC network to simulate all sub-node states for voltage/current and to generate EMIR reports.
  • Integration with the Cadence Virtuoso® platform, providing a single design flow for better productivity in the analog and custom block EMIR signoff process
  • Integration with Voltus IC Power Integrity Solution, resulting in a seamless flow for advanced analog/mixed-signal power signoff for designs that have mixed transistor-level and cell-level blocks
Fastest Design Closure Flow
The combined use of Voltus-Fi Custom Power Integrity Solution and Voltus IC Power Integrity Solution, tightly integrated with several other Cadence tools, provides the industry’s fastest design closure flow.
  • Get a unified electrical signoff flow with Cadence Tempus™ Timing Signoff Solution and Quantus™ QRC Extraction Solution
  • Bring power grid design to the early stage of physical implementation with an early rail analysis capability via the Cadence Encounter® Digital Implementation System
  • Get accurate IC power integrity analysis, driven by real-world power simulation vectors, with Cadence Palladium® technology
  • Benefit from chip-package-PCB co-simulation and analysis with Cadence Allegro® Sigrity® technology

 

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