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Tempus Timing Signoff Solution 


Massively parallelized timing analysis and physically aware multi-mode, multi-corner optimization for faster design closure and signoff

Cadence® Tempus™ Timing Signoff Solution is a complete standalone tool that delivers silicon-accurate timing signoff and signal integrity analysis that ensures operational chips after tapeout. By tightly coupling the design implementation environment with the timing signoff environment, the Tempus solution enhances timing convergence throughout the design flow and greatly reduces the time to design closure.
33 resources found
 
Title Type Rated
Techniques to Accelerate Power and Timing Signoff of Advanced-Node SoCs White Paper
Format: .PDF    Date: 15 Sep 2014
White Paper
 3
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Addressing Test Cost Challenges in LPCT Designs White Paper
Format: .PDF    Date: 13 Aug 2014
White Paper
 9
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Cadence QuickView Layout and Manufacturing Data Viewer Datasheet
Format: .PDF    Date: 22 Jul 2014
Datasheet
 13
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Quantus QRC Extraction Solution Datasheet
Format: .PDF    Date: 14 Jul 2014
Datasheet
 21
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How to Speed Signoff Extraction by 5X with Next-Generation Extraction Tool White Paper
Format: .PDF    Date: 14 Jul 2014
White Paper
 3
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Hierarchical Timing Analysis: Pros, Cons, and a New Approach White Paper
Format: .PDF    Date: 11 Apr 2014
White Paper
 2
Recommend!
Solutions for Mixed-Signal SoC Verification Using Real Number Models White Paper
Format: .PDF (1.8MB)    Date: 19 Nov 2013
White Paper
 7
Recommend!
How to Achieve 10X Faster Power Integrity Analysis and Signoff White Paper
Format: .PDF (1.2MB)    Date: 12 Nov 2013
White Paper
 4
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A Call to Action: How 20nm Will Change IC design White Paper
Format: .PDF (1.3MB)    Date: 08 Feb 2013
White Paper
 10
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Taming the Challenges of 20nm Custom/Analog Design White Paper
Format: .PDF (1.4MB)    Date: 09 Nov 2012
White Paper
 3
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Encounter Diagnostics Datasheet
Format: .PDF (1.4MB)    Date: 28 Jun 2012
Datasheet
 10
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Cadence Physical Verification System Datasheet
Format: .PDF    Date: 31 Jan 2012
Datasheet
 14
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Interactive Short Locator: Establishing Efficiency and Predictability in the LVS Short Debug Process for Advanced SoC Designs Technical Paper
Format: .PDF (1.5MB)    Date: 30 Jan 2012
Technical Paper
 3
Recommend!
Modeling Stress-Induced Variability Optimizes IC Timing Performance White Paper
Format: .PDF    Date: 08 Dec 2011
White Paper
 1
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Cadence DFM services Datasheet
Format: .PDF (1.5MB)    Date: 11 Oct 2011
Datasheet
 16
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EDA360: The Way Forward for Electronic Design Vision Paper
Format: .PDF (1.9MB)    Date: 15 Apr 2010
White Paper
 3
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Assura Physical Verification Datasheet
Format: .PDF    Date: 01 May 2009
Datasheet
 23
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Cadence MaskCompose Reticle and Wafer Synthesis Suite Datasheet
Format: .PDF    Date: 05 Aug 2008
Datasheet
 15
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Implementing the Fastest Path from Concept to Consumer for Advanced-Node ICs White Paper
Format: .PDF    Date: 01 Apr 2008
White Paper
 8
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Cadence Litho Physical Analyzer Datasheet
Format: .PDF    Date: 01 Apr 2008
Datasheet
 5
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