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Tempus Timing Signoff Solution 

Massively parallelized timing analysis and physically aware multi-mode, multi-corner optimization for faster design closure and signoff

Cadence® Tempus™ Timing Signoff Solution is a complete standalone tool that delivers silicon-accurate timing signoff and signal integrity analysis that ensures operational chips after tapeout. By tightly coupling the design implementation environment with the timing signoff environment, the Tempus solution enhances timing convergence throughout the design flow and greatly reduces the time to design closure.
Cadence Delivers Unprecedented Performance and Capacity in Timing Signoff and Closure.
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The Tempus Timing Signoff Solution provides full-chip static timing analysis (STA) with gate-level delay calculation, signoff-level timing and signal integrity (SI) analysis, statistical timing and leakage analysis, advanced on-chip variation analysis, and the advanced node functionality required for double-patterning and waveform effects.

The solution removes the iteration bottleneck by providing a consistent, integrated Common Timing Engine for both the design implementation stage and the final timing verification stage of the design cycle. As a result, you get correlation and convergence between implementation and signoff for faster timing closure.

  • Advanced timing solution with comprehensive analysis
    • Delay calculation
    • STA
    • SI analysis
    • Statistical timing analysis
    • On-chip variation analysis
  • Integrated with Cadence Encounter® Digital Implementation System
    • Consistent timing analysis during implementation throughout the flow and signoff at the end of the flow
    • Faster design convergence and timing closure with smaller design margin
    • Common database infrastructure for fast setup and a consistent usage model throughout the flow
  • Unmatched timing signoff accuracy
    • Path-based analysis for pessimism reduction
    • Prevention of excessive over-design to exceed performance, power, and area targets
    • Accurate base delay and SI delay calculation to within 2-5% of SPICE
    • Leveraging of current source models for greater accuracy on mainstream and advanced node designs
    • Built-in critical path simulation for delay and SI correlation with SPICE
  • Higher throughput for shorter design cycles and faster time to design signoff
    • Parallel processing for higher throughput
    • End-to-end multi-threaded timing and SI analysis for faster signoff turnaround
    • Concurrent multi-mode/multi-corner (MMMC) timing and SI analysis for large view-count designs
    • Distributed multi-CPU and multithreaded processing for maximum hardware utilization
  • Higher productivity to shorten tapeout schedules by weeks
    • Industry-renowned global timing debug to accelerate root-cause and bottleneck analysis
    • Physically aware engineering change order (ECO) optimization for MMMC
    • MMMC-aware timing debug for quick timing issue identification across all views
    • MMMC signoff ECO optimization and repair across all timing views for fewer ECO cycles
  • Support of major foundries, ASIC, and IP vendors, and exclusive use by multiple IDMs for signoff


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