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QuickView Signoff Data Analysis Environment 


Full-chip view, review, integrate, edit, superimpose layout and manufacturing data in multiple formats, and tape out

Cadence® QuickView Signoff Data Analysis Environment is the industry’s production-proven full-chip high-performance, high-capacity data-viewing, and standalone chip-finishing system that supports multiple formats of design, layout, and manufacturing data.

QuickView Signoff Data Analysis Environment Datasheet »

Product ImageThe QuickView Signoff Data Analysis Environment is an easy-to-use, high-performance, and standalone chip-finishing system that supports multiple formats of design, layout, and manufacturing data. The QuickView Signoff Data Analysis Environment loads large layouts (GDSII, OASIS, LEF/DEF, and manufacturing formats) in seconds, and provides a rich set of debugging features, including net connectivity tracing, visualization, overlay, and GDSII/OASIS editing.

Features/Benefits
  • Multi-format display enables viewing and superimposing of design data in any of its intermediate conditions throughout the chip-finishing process
  • High-performance, high-capacity data viewing with powerful options that allow the full range of display, from deep sub-micron features to full reticle or mask-level databases
  • Intelligent overlay and graphical XOR capabilities make graphical comparisons of data easy by providing an additional element of decision support
  • Robust signoff analysis and chip-finishing environment
  • Fast and flexible database operations
  • Seamless integration with Cadence Physical Verification System (PVS) enables DRC/LVS/ERC job submission, error analysis, and review within a single environment
  • Interactive LVS/ERC data (cross) probing on large layouts and error databases

 

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