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Cadence CMP Predictor

Predict and optimize interconnect thickness and chip topography variability

Cadence CMP Predictor enhances design performance and yield through model-based CMP hotspot detection and CMP-aware RC extraction.

Cadence® CMP Predictor turns the uncertainty of manufacturing process variation into predictable impacts, and then minimizes these impacts during the design stage. It provides full-chip, multi-level interconnect thickness and topography predictions for copper electrochemical deposition (ECD) and copper/dielectric chemical-mechanical planarization (CMP) processes.

CMP-related hotspots, such as copper pooling, can have detrimental effects on chip yield. The conventional rules-based approach to hotspot detection fails to capture long-range and multi-level CMP effects. Cadence CMP Predictor uses a highly accurate model-based approach to finding potential hotspot areas. It also feeds the thickness and topography variation data into extraction tools, enabling better RC and timing analysis.

Features/Benefits

Accurately predicts multi-layer thickness and topography variability using a model-based approach
Identifies potential problem areas (hotspots) that affect yield
Minimizes or eliminates hotspots through integration with Cadence Chip Optimizer
Interfaces with Cadence QRC Extraction to identify timing-related problems (such as race conditions) and potentially reduce process guardbands