Cadence.com will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST).
Cadence.com login, registration, community posting and commenting functionalities will be disabled.
Home > Tools > Silicon Signoff and Verification > Cadence CMP Predictor

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Company Location *

Comments: *

Cadence CMP Predictor 


Predict and optimize interconnect thickness and chip topography variability

Cadence CMP Predictor enhances design performance and yield through model-based CMP hotspot detection and CMP-aware RC extraction.

Product ImageCadence® CMP Predictor turns the uncertainty of manufacturing process variation into predictable impacts, and then minimizes these impacts during the design stage. It provides full-chip, multi-level interconnect thickness and topography predictions for copper electrochemical deposition (ECD) and copper/dielectric chemical-mechanical planarization (CMP) processes.

CMP-related hotspots, such as copper pooling, can have detrimental effects on chip yield. The conventional rules-based approach to hotspot detection fails to capture long-range and multi-level CMP effects. Cadence CMP Predictor uses a highly accurate model-based approach to finding potential hotspot areas. It also feeds the thickness and topography variation data into extraction tools, enabling better RC and timing analysis.

Features/Benefits
  • Accurately predicts multi-layer thickness and topography variability using a model-based approach
  • Identifies potential problem areas (hotspots) that affect yield
  • Minimizes or eliminates hotspots through integration with Cadence Chip Optimizer
  • Interfaces with Cadence QRC Extraction to identify timing-related problems (such as race conditions) and potentially reduce process guardbands

 

 Content Query Web Part ‭[4]‬