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Manufacturability Signoff
Litho-aware design
With the advent of 45nm process technologies, systematic variations due to lithography must be taken into account during SoC, ASIC, and custom design. Cadence
®
litho-aware design solutions help designers prevent catastrophic failures due to lithography during routing, detect them using foundry-certified model-based solutions, and automatically repair them. Assured that what they design is what they will get on silicon, design teams can maximize yield, improve chip performance, and eliminate costly silicon re-spins.
Cadence Litho Physical Analyzer
Detects and corrects lithography hotspots. Uses a model-based technology to predict silicon contours quickly and accurately. Improves parametric yield and chip performance.
Learn more
»
Cadence Litho Electrical Analyzer
Extracts device and interconnect electrical behavior from contours. Detects and repairs timing and leakage hotspots due to systematic variations.
Learn more
»
CMP-aware design
Thickness variation due to chemical-mechanical planarization (CMP) can lead to physical or electrical failures, and needs to be analyzed before silicon is manufactured. Cadence
®
CMP-aware design technology offers a model-based approach to accurately predict multi-layer thickness variability. Using intelligent fill and concurrent multi-corner timing optimization methods, designers can pro-actively assess the impact of CMP on their designs and minimize physical and parametric yield issues.
Cadence CMP Predictor
Enhances design performance and yield through model-based CMP hotspot detection and CMP-aware RC extraction.
Learn more
»
Physical verification
Typically known as design rule checking (DRC) and layout vs. schematic (LVS), physical verification ensures that spatial and other physical rules given by the foundry are followed in a given layout. Cadence
®
physical verification technology enables fast, silicon-accurate, foundry-certified DRC and LVS for any type of design—standard cell, IP, block, or full chip.
Cadence Physical Verification System
Offers a front-to-back design, implementation, and signoff flow in a single solution. Speeds turnaround of design rule check and layout versus schematic verification.
Learn more
»
Assura Physical Verification
Performs design rule checking and layout vs. schematic verification to deliver high-yielding custom IP for SoC designs.
Learn more
»
Chip optimization
Conventional IC implementation tools create oversimplified models of interconnect. Cadence
®
chip optimization technology uses an innovative space-based approach to address the most demanding sub-wavelength lithography and manufacturing process rules. It optimizes layout based on electrical constraints, manufacturing rules, and timing objectives to improve manufacturability, yield, and performance.
Cadence Chip Optimizer
Uses a 3D space-based approach that models, analyzes, and optimizes layout based on electrical constraints, manufacturing rules, and objectives.
Learn more
»
Silicon diagnostics
With the increasing number of subtle design-process interactions at advanced technology nodes, yield loss is a growing challenge. Promoting accurate identification of physical layout topologies involved in yield loss, Cadence
®
silicon diagnostics technology accelerates yield ramp on devices fabricated at 90nm and below. Engineers can quickly analyze hundreds of failures, identify the source of systematic yield loss, and pinpoint defect locations in the netlist and layout to optimize designs and ensure the highest yield.
Encounter Diagnostics
Accelerates yield ramp by analyzing results from manufacturing test to find systematic failures and pinpoint their location within the design layout.
Learn more
»
Design for yield
To achieve high-yield goals quickly, designers must detect and correct random defects and make tradeoffs among timing, area, and power. Cadence
®
design-for-yield technology offers fast and flexible feasibility analysis, giving engineers an early, accurate view of whether complex designs will meet their targets and be physically realizable. With silicon-correlated defectivity models, design teams can analyze failures and optimize their designs to reduce physical yield loss before tapeout.
Encounter Digital Implementation System
Encounter Digital Implementation System delivers a complete solution for variation- and manufacturing-aware design closure, low power, mixed-signal implementation, and integrated signoff in a single, scalable multi-CPU-enabled design environment for high-capacity, high-performance digital implementation.
Learn more
»
Mask data preparation
To speed production and reduce errors in the tapeout flow, engineers need the latest resolution enhancement technology (RET) and optical proximity correction (OPC) capabilities. Cadence
®
technology offers an advanced, concurrent process and proximity compensation solution for OPC, plus the industry’s most widely used mast data preparation and silicon analysis solutions, endorsed by leading foundries for all nanometer process nodes.
Cadence MaskCompose Reticle and Wafer Synthesis Suite
Automates and optimizes reticle and wafer synthesis to eliminate errors and reduce mask-making cycle times.
Learn more
»
Cadence QuickView Layout and Manufacturing Data Viewer
Allows engineers to view and superimpose manufacturing data in various industry-standard formats.
Learn more
»
Assura Physical Verification
Performs design rule checking and layout vs. schematic verification to deliver high-yielding custom IP for SoC designs.
Learn more
»
Cadence Chip Optimizer
Uses a 3D space-based approach that models, analyzes, and optimizes layout based on electrical constraints, manufacturing rules, and objectives.
Learn more
»
Cadence CMP Predictor
Enhances design performance and yield through model-based CMP hotspot detection and CMP-aware RC extraction.
Learn more
»
Cadence Litho Electrical Analyzer
Extracts device and interconnect electrical behavior from contours. Detects and repairs timing and leakage hotspots due to systematic variations.
Learn more
»
Cadence Litho Physical Analyzer
Detects and corrects lithography hotspots. Uses a model-based technology to predict silicon contours quickly and accurately. Improves parametric yield and chip performance.
Learn more
»
Cadence MaskCompose Reticle and Wafer Synthesis Suite
Automates and optimizes reticle and wafer synthesis to eliminate errors and reduce mask-making cycle times.
Learn more
»
Cadence Physical Verification System
Offers a front-to-back design, implementation, and signoff flow in a single solution. Speeds turnaround of design rule check and layout versus schematic verification.
Learn more
»
Cadence QuickView Layout and Manufacturing Data Viewer
Allows engineers to view and superimpose manufacturing data in various industry-standard formats.
Learn more
»
Encounter Diagnostics
Accelerates yield ramp by analyzing results from manufacturing test to find systematic failures and pinpoint their location within the design layout.
Learn more
»
Encounter Digital Implementation System
Encounter Digital Implementation System delivers a complete solution for variation- and manufacturing-aware design closure, low power, mixed-signal implementation, and integrated signoff in a single, scalable multi-CPU-enabled design environment for high-capacity, high-performance digital implementation.
Learn more
»
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