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Silicon Signoff and Verification 

GLOBALFOUNDRIES
Luigi Capodieci
GLOBALFOUNDRIES

Luigi Capodieci, Director of Design for Manufacturing, R&D Fellow at GLOBALFOUNDRIES, discusses how they collaborated with Cadence on pattern-matching technologies to accelerate full-chip DFM signoff.

IBM
Lars Liebman
IBM

Lars Liebman, Distinguished Engineer at IBM, highlights the collaboration between IBM and Cadence in solving design challenges at 20nm and 14nm technology nodes.

S3
S3
Flavio Cali

Hear from Flavio Cali with S3 Group, as he highlights the user experience of Cadence Physical Verification System (PVS) for SoC design.

Silicon Blue Technologies
Andrew Chan
Silicon Blue Technologies

Andy Chan, Vice President of Engineering at Silicon Blue Technologies details how they utilize the TSMC-certified Cadence DFM Services along with Cadence technologies to develop consumer mobile applications.

SMIC
Li-Fu Chang
SMIC

Li-Fu Chang, SoC Technology Development Director at SMIC describes the joint effort of SMIC with Cadence in creating DFM-clean libraries and accurate IP, CMP, and litho models for their worldwide customer base.

STMicroelectronics
Karl Herterich
STMicroelectronics

At STMicroelectronics, engineers were presented with a design in the C model, yet the register-transfer level (RTL) would not become available for another five to six weeks. The engineers wanted to make use of this time and start their verification process. In this short video, Karl Herterich, senior IC verification engineer at the company, explains how Cadence and its Incisive® Specman Elite® Testbench helped the team adjust its verification environment so it could work on the C model first, then RTL for signoff. STMicroelectronics gained a shorter verification cycle in the process.

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