Power Is Now a Primary Design Constraint
Whether designing the smallest handheld wireless device, the latest consumer electronics product, or a networking and high-performance computing solution, power is now a key consideration for all designs. IC power consumption significantly impacts the designer’s ability to differentiate a product based on features, cost, performance, time to market, and even reliability.
With this shift in focus, power is now a primary design constraint, joining the traditional constraints of timing and area. This means that a successful design environment and methodology must simultaneously consider all design constraints (including power) in a seamless closed-loop, multi-objective planning-to-signoff solution. Addressing these needs is essential, regardless of the types of power reduction techniques that are being applied: basic techniques (multi-VT libraries and clock gating), more advanced techniques (dynamic voltage/frequency scaling and power shut-off), or emerging techniques (back-bias and low-swing clocks). Whichever combination of techniques will be applied, design teams must actively measure and manage risk while maintaining productivity levels.
An integrated solution for planning, design, verification, and implementation
The Cadence Low-Power Solution provides a complete design-to-signoff methodology that begins with early design planning and system architecture then continues through front-end design, functional verification, synthesis, physical implementation, packaging, and signoff. Since many designs need to integrate and add power control to analog and mixed-signal IP, the solution supports mixed-signal designs across this entire flow, ensuring consistency and convergence.
Our comprehensive flow includes power exploration, estimation, and analysis at every step including C-level design exploration, software optimization, RTL synthesis, and signoff. Along with the implementation flow, power verification is utilized to enable first-pass success. By leveraging static, dynamic, and formal power verification techniques in a closed-loop verification methodology, design teams can eliminate last-minute power-related surprises.
This fully integrated, highly automated, power-aware solution is backed by industry-leading Cadence Services and the industry's largest power-focused industry alliances (Power Forward Initiative and SI2's Low Power Coalition). Through its advanced low-power services (ALPS) initiative, Cadence Services continues to invest in and develop new low-power technologies, and then works with customers to deploy them—first-time right—on their latest designs for the lowest power.
The Cadence Low-Power Solution:
- Reduces risk: By minimizing the need for manual intervention and using a robust estimation and verification methodology, design teams can eliminate silicon risks resulting from functional and structural flaws.
- Boosts productivity: With integrated estimation, logic design, verification, implementation automation, and signoff technologies, design teams maintain high productivity levels.
- Speeds time to market: By reducing the number of iterations within the flow and limiting silicon re-spins, design teams can achieve time-to-market requirements predictably.
- Increases quality of silicon: Through easy-to-use "what-if" exploration early in the design flow, designers can identify optimal power architectures to achieve desired specifications. Throughout the implementation flow, advanced multi-objective optimization engines help designers make superior tradeoffs among timing, power, and area targets.