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Encounter True-Time ATPG 

Automatic power- and timing-aware test generation

Delivers the industry’s most comprehensive automated test pattern generation (ATPG) solution. Through a broad array of pre-defined and user-defined static and transition-based faults, multiple on-chip compression architectures, and power-aware test capabilities, Encounter True-Time ATPG achieves the most stringent quality and cost goals.

Encounter True-Time ATPG Datasheet »
Choosing the right scan architecture for your design white paper »
Leveraging Physically Aware Design-for-Test white paper »

Cadence® Encounter® True-Time ATPG offers robust automated test pattern generation (ATPG) engines that generate tests for all standard design-for-test (DFT) methods and flows. It provides intelligent ATPG with compression to reduce scan test time while maintaining the highest test coverage. With its onboard timing-aware and power-aware engine, and by using circuit timing information, True-Time ATPG supports both stuck-at and transition fault models and automatically generates high-coverage static and timing-accurate delay test patterns to uncover small delay defects in deep submicron designs.

True-Time ATPG's patented pattern-fault technology raises the bar in fault detection by providing advanced capabilities for defect-based modeling. This is crucial in advanced process nodes where silicon defects are more subtle. Two example uses are net bridging effects and gate exhaustive fault modeling.

True-Time ATPG is available in Basic and Advanced configurations.

  • Ensures high quality of shipped silicon with production-proven 2-4X reduction in test escapes
  • Provides superior partial scan coverage with proprietary pattern fault modeling and sequential ATPG algorithms
  • Optimizes test coverage with random resistive fault analysis (RRFA) and deterministic fault analysis (DFA) test-point insertion methodology
  • Boosts productivity by integrating with Encounter RTL Compiler
  • Delivers superior runtime throughput with high-performance model build and fault simulation engines as well as distributed ATPG processing
  • Lowers cost of test with pattern compaction and compression techniques that maintain full scan coverage
  • Balances tester costs with diagnostics methodologies by offering flexible compression architectures with full X masking capabilities (including MISR and XOR-based solutions)
  • Supports low pin-count testing via JTAG control of memory built-in self test (MBIST) and high-compression ratio technology
  • Supports reduced pin-count testing for I/O test
  • Interfaces with Encounter Power System for accurate power calculation and pattern IR drop analysis
  • Reduces circuit and switching activity during manufacturing test to manage power consumption
  • Reduces false failures due to voltage drop
  • Provides a GUI with powerful interactive analysis capabilities including a schematic viewer and sequence analyzer