Generate power-aware, timing-aware tests automatically and efficientlyWith Encounter True-Time ATPG’s compact, high-coverage, high-quality sets of manufacturing tests optimized for power, you can reduce cost of test and achieve high-quality silicon. Encounter True-Time ATPG Datasheet » |
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Cadence® Encounter® True-Time ATPG offers robust automated test pattern generation (ATPG) engines that generate tests for all standard design-for-test (DFT) methods and flows. It provides intelligent ATPG with compression to reduce scan test time while maintaining the highest test coverage. With its onboard timing-aware and power-aware engine, and by using circuit timing information, True-Time ATPG supports both stuck-at and transition fault models and automatically generates high-coverage static and timing-accurate delay test patterns to uncover small delay defects in deep submicron designs. True-Time ATPG’s patented pattern fault technology raises the bar in fault detection by providing advanced modeling capabilities (including RAM modeling) for proven pass-through test and defect-based modeling. Its gate-exhaustive coverage (GEC) model and pattern generation methodology is superior to N-Detect methods in both efficiency and effectiveness (production-proven) for capturing gate-intrinsic defects. Its low-power test capability minimizes the costly impact of average and instantaneous test-mode power consumption on yield and product reliability. True-Time ATPG is available in Basic and Advanced configurations.
Features/Benefits
- Delivers highest quality of shipped silicon with a proven 2x reduction in defects per million
- Offers superior partial scan coverage with proprietary fault modeling and sequential ATPG algorithms
- Increases productivity with high-performance fault simulation engines
- Offers pattern reuse capabilities
- Supports advanced modeling (pattern fault, memory, latch-based) for complex designs
- Reduces cost of test with pattern compaction and compression techniques that maximize coverage with compact vector sets
- Supports multiple compression architectures to for maximum flexibility and minimum cost of ownership
- Reduces circuit activity during manufacturing test to lower power consumption for both full-scan and compression modes
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