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Encounter DFT Architect 

Full-chip, synthesis-based, power-aware test architecture development

With its synthesis-based, unified methodology for creating full-chip logic and memory tests, Cadence® Encounter® DFT Architect addresses and optimizes multiple design and manufacturing objectives—such as timing, area, power, congestion, and test coverage—for today’s complex ICs and system-on-chip (SoC) designs.

Encounter DFT Architect Datasheet »
Choosing the right scan architecture for your design white paper »
Leveraging Physically Aware Design-for-Test white paper »

Part of the Encounter Test family, Encounter DFT Architect is the industry’s first full-chip, synthesis-based, power-aware test architecture development product with top-down, bottom-up hierarchical design support. It is a key component of a true global synthesis environment where logic and design-for-test (DFT) constructs are compiled in a single pass for concurrent optimization of timing, area, wiring congestion, and power. This single environment—with advanced rule checking, structure verification, coverage optimization, and analysis—ensures the highest quality automated test pattern generation (ATPG)-ready netlist with an advanced full-chip test infrastructure.

Industry-leading power management techniques and testing of low-power functional modes make the combination of Encounter DFT Architect and Encounter True-Time ATPG the most robust, power-aware ATPG technology on the market. Integration with Encounter RTL Compiler global synthesis and the Common Power Format (CPF) allows users to create, insert, hierarchically connect, and verify test structures according to user specification. This unified methodology for “design-with-test” maximizes ease of use and accelerates the development of a higher-quality test infrastructure at lower cost.

Test architectures supported include full and partial scan, scalable test compression (XOR and MISR), hierarchical compression, low pin count compression with SmartScan, memory built-in self test (MBIST) with predefined and custom test algorithm support, logic BIST (LBIST), on-product clock generation (OPCG), boundary scan (IEEE1149.1/6), I/O test, IEEE 1500 core wrapping, stacked-die die wrapping for 3D ICs, power-aware DFT, and ATPG.

  • Performs concurrent logic and DFT synthesis across area, timing, wiring congestion, and power parameters
  • Boosts productivity from RTL to ATPG by moving test decisions, structure verification, and analysis to the front end
  • Accelerates development of a higher-quality IC test infrastructure for transition defect testing, including auto-generation and insertion of OPCG macros and ATPG protocol files
  • Performs automatic IC test infrastructure insertion and verification from a single specification and environment
  • Supports hierarchical and flat design flows
  • Eliminates errors caused by manual stitching and integration
  • Power-aware DFT inserts specialized test control structures, and validates and tests all power modes
  • Power-aware ATPG with early power estimation capabilities identify power issues during test mode and eliminate costly iterations
  • Performs physically aware scan placement and ordering as well as test compression-logic physical optimization
  • Test coverage optimization enables early testability analysis and test point insertion to improve test pattern volume and test coverage for manufacturing test and LBIST
  • Fully integrated MBIST solution optimizes memory test development time and reduces project costs
  • Fully integrated LBIST solution ideal for automotive applications with low area overhead and efficiency to decide tradeoff between runtime and coverage
  • Flexible compression architectures (MISR, XOR, or hybrid) dramatically reduce manufacturing test cost, increase throughput, and optimize diagnostic flows
  • Advanced masking architectures ensure the highest compression while maintaining full scan coverage
  • Supports efficient low pin-count test solutions for multi-site testing