Creating a complete manufacturing test methodology typically requires post-netlist use of standalone software products—a tedious and error-prone process that results in lower quality netlists, inadequate test coverage, extra post-synthesis iterations, and higher test and production costs.
Cadence® Encounter® DFT Architect is the industry’s first full-chip, truly synthesis-based, power-aware test architecture design technology. It supports full and partial scan, JTAG (1149.1/6) insertion and verification, and I/O test, as well as flexible, scalable, low-pin, and bottom-up hierarchical compression architectures that can support multi-site wafer test. Encounter DFT Architect also supports BIST solutions, optimizes both pre- and post-synthesis test coverage, and automates on-product clock generation (OPCG) and script generation for static and transition-based test patterns (ATPG).
With DFT Architect, design teams can create a high-quality test infrastructure for either hierarchical or flat deep-submicron designs. It enables a unified specify-insert-verify methodology for a design-with-test infrastructure, including low-power and multi-supply/multi-voltage designs. To maximize ease-of-use and test quality while reducing development time and test cost, DFT Architect’s advanced features are now implemented natively with Encounter RTL Compiler global synthesis. This integration allows users to create, insert, hierarchically connect, and verify test structures according to specification, including the most stringent low-power specs using the Common Power Format (CPF). This integration also offers an advanced GUI for efficient RTL and gate-level debug and auto-fix capabilities with traceability back to RTL.
DFT Architect is available in Basic and Advanced configurations.
Features/Benefits
- Speeds the development and implementation of high-quality test infrastructures
- Enables concurrent logic and test infrastructure insertion and verification from a single specification
- Automation eliminates errors due to manual stitching and integration
- Testability optimization delivers higher test coverage with early testability analysis via ATPG links
- Increases predictability by moving test decisions to the front-end flow
- Supports bottom-up hierarchical and flat design flows
- Complies with IEEE 1149.1 and 1149.6 for robust test access capabilities
- Reduces development costs with one-pass logic and DFT synthesis
- Reduces test costs with flexible compression architectures and a one-pass diagnostics methodology
- Supports low-power design techniques to enable power-aware test and power-aware ATPG