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Encounter DFT Architect 

Full-chip, synthesis-based, power-aware test architecture development

With its synthesis-based, unified methodology for creating full-chip logic and memory tests, Cadence® Encounter® DFT Architect addresses and optimizes multiple design and manufacturing objectives—such as timing, area, power, congestion, and test coverage—for today’s complex ICs and system-on-chip (SoC) designs.

Encounter DFT Architect Datasheet »
Choosing the right scan architecture for your design white paper »
Leveraging Physically Aware Design-for-Test white paper »
2 resources found
Title Type Rated
Expanding Manufacturing Verification to the Real World with LBIST
Format: .PDF    Date: 20 May 2014
White Paper
Encounter DFT Architect Datasheet
Format: .PDF    Date: 02 Jan 2013