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Encounter RTL Compiler Advanced Physical Option 

Physically aware synthesis for faster convergence on design goals

Enables logic designers to account for physical interconnect—without having to learn how to do physical design.

Encounter RTL Compiler Advanced Physical Option Datasheet »
Cadence® Encounter® RTL Compiler Advanced Physical Option delivers real physical interconnect timing to the logic synthesis environment. Its high-capacity global synthesis, combined with the Encounter Digital Implementation System’s production placement engine, helps logic design teams easily predict, visualize, and fix physical issues that affect closure on a project’s performance, power, and area intent. Encounter RTL Compiler Advanced Physical Option speeds physical design closure by improving predictability and convergence on silicon quality goals through a robust suite of physically aware (PA) features.

  • Improves predictability of physical design closure
    • Realistic interconnect timing in synthesis means that when goals are met in synthesis, they will also converge in physical design
    • Handoff of legal placement enables the physical design team to start with exactly the same model on which the logic design team signed off
    • Modeling routing congestion during synthesis at a higher level of abstraction helps structure logic to avoid actual congestion issues later on during the routing stage
  • Increases overall quality of silicon
    • Accurately focuses performance optimization on the truly timing-critical logic through register-transfer level (RTL) physically aware mapping (PAM)
    • Predicts and eases congestion in datapath-intensive designs by using physically aware structuring (PAS)
    • Reduces power consumption by eliminating the need to apply excessive performance margin
    • Lowers clock power without impacting timing/congestion by merging single registers into multi-bit registers through physically aware multi-bit cell inferencing (PA-MBCI)
    • Synthesizes at the physical partition level with abstracted physical interconnect timing for the broadest scope of optimization
    • Performs physical optimizations earlier in the implementation process for larger-scale improvements
    • Analyzes and fixes scan chain ordering inefficiencies and reduces ATPG compression/decompression congestion through physically aware DFT (PA-DFT)
  • Reduces schedule risk
    • Eliminates iterations between logic and physical design teams caused by large differences in interconnect timing models
    • Provides early insight into potential congestion issues that can occur during routing
  • Ease of use enables widespread adoption by logic designers
    • Utilizes the same synthesis use model and user interface to which logic designers are accustomed
    • Physical interconnect modeling gives logic designers early insight into problems physical designers will encounter, enforcing smarter RTL design
    • Increases communication between logic and physical design teams