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Encounter RTL Compiler 


Global synthesis that enables concurrent optimization of timing, area, and power intent

Encounter® RTL Compiler offers a unique set of patented global-focus algorithms that perform true top-down global RTL design synthesis to accelerate silicon realization. With concurrent multi-objective optimization (timing, area, and power intent) and support for advanced low-power design techniques, Encounter RTL Compiler reduces chip power consumption while meeting frequency goals. An Advanced Physical Option provides physically aware synthesis capabilities so that logic designers can account for the physical interconnect, without having to learn how to do physical design.

Encounter RTL Compiler Datasheet »
Encounter RTL Compiler Advanced Physical Option Datasheet »
EE Journal Chalk Talk: Physically Aware Synthesis Techniques »
51 resources found
 
Title Type Rated
Leveraging Physically Aware Design-for-Test to Improve Area, Power, and Timing White Paper
Format: .PDF (4MB)    Date: 27 Jan 2015
White Paper
 0
Recommend!
Encounter RTL Compiler Datasheet
Format: .PDF    Date: 03 Jan 2014
Datasheet
 22
Recommend!
Encounter RTL Compiler Compiler Advanced Physical Option Datasheet
Format: .PDF    Date: 03 Jan 2014
Datasheet
 19
Recommend!
Meeting Failure Rate Goals in Automotive Electronics Technical Brief
Format: .PDF    Date: 25 Nov 2013
Technical Brief
 3
Recommend!
Cadence and Sharp Success Story
Format: .PDF    Date: 14 Nov 2012
Success Story
 3
Recommend!
Cadence and NetEffect Success Story
Format: .PDF    Date: 11 Jul 2012
Success Story
 1
Recommend!
Eliminating Routing Congestion Issues with Logic Synthesis White Paper
Format: .PDF    Date: 15 Dec 2011
White Paper
 11
Recommend!
Technical University of Braunschweig and Cadence Success Story
Format: .PDF    Date: 07 Dec 2011
Success Story
 2
Recommend!
Cadence and Sound Design Technologies Success Story
Format: .PDF    Date: 19 Apr 2010
Success Story
 3
Recommend!
Archived webinar - How Logic Designers Can Avoid Congestion Nightmares
Date: 24 Sep 2009
Webinar
 1
Recommend!
Global Synthesis for Design Closure White Paper
Format: .PDF    Date: 03 Dec 2008
White Paper
 11
Recommend!
Practical Guide to Low-Power Design - User Experience with CPF
Date: 16 May 2008
eBook
 45
Recommend!
Low-Power Methodologies in a Multi-Core Networking Chip
Format: .PDF (1.4MB)    Date: 05 Mar 2008
Conference Paper
 3
Recommend!
Learn to Optimize Your Low-Power Design Process
Format: .PDF    Date: 04 Jan 2008
Cadence Article
 5
Recommend!
HW/SW Co-Simulation
Format: .PDF    Date: 04 Nov 2007
Conference Paper
 8
Recommend!
Timing closure on a 1GHz DSP-processor using RTL Compiler and SoC Encounter
Format: .PDF    Date: 04 Nov 2007
Conference Paper
 6
Recommend!
Verification of Low-Power Designs using CPF
Format: .PDF    Date: 23 Oct 2007
Conference Paper
 3
Recommend!
RTL Compiler Optimization on Full Chip Complex SoC design
Format: .PDF    Date: 17 Oct 2007
Conference Paper
 5
Recommend!
Predicting Physical Design Results Using Advanced Synthesis Features
Format: .PDF (1.8MB)    Date: 27 Sep 2007
Conference Paper
 2
Recommend!
Speeding up HW/SW Co-Development using HW Emulation
Format: .PDF    Date: 15 Sep 2007
Conference Paper
 5
Recommend!