Global synthesis that enables concurrent optimization of timing, area, and power intentEncounter RTL Compiler allows engineers to look across the entire design as they employ concurrent optimization techniques, such as making tradeoffs among timing, area, and power intent to converge on realizable silicon.  Encounter RTL Compiler Datasheet » |
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 To maximize performance, decrease die size, and reduce power consumption without compromising schedule, designers need a global synthesis solution that enables concurrent optimization of timing, area, and power intent. Encounter® RTL Compiler, a key component of the Cadence Logic Design and Verification Solution for silicon realization, provides production-proven global synthesis that quickly converges on requirements for faster, smaller, and lower-power chips. With its unique set of patented global-focus algorithms, combined with new physically-aware optimization and analysis abstracted to the logical RTL level, Encounter RTL Compiler cuts design time while ensuring the highest quality of silicon.
Features/Benefits
- A well-balanced logic structure isolates critical paths and reduces power, area, and congestion in off-critical logic
- Enables faster timing closure and convergence through optimized place-and-route
- Physical layout estimation eliminates the need for wireload models
- Integration with First Encounter® Silicon Virtual Prototyping provides real physical timing to logic optimization and analysis
- Reduces power consumption through single-pass multi-Vt optimization, hierarchical and multi-stage clock gating, MSV support, power shutoff, and state-retention power gating
- Shrinks die sizes with multi-objective optimization
- Speeds up time to design closure with multi-mode synthesis optimization and analysis
- Increases productivity by enabling chip-level synthesis and eliminating manual partitioning, budgeting, and reassembly
- Uses standard inputs and outputs to ease adoption
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