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Encounter RTL Compiler 

Global synthesis that enables concurrent optimization of timing, area, and power intent

Encounter® RTL Compiler offers a unique set of patented global-focus algorithms that perform true top-down global RTL design synthesis to accelerate silicon realization. With concurrent multi-objective optimization (timing, area, and power intent) and support for advanced low-power design techniques, Encounter RTL Compiler reduces chip power consumption while meeting frequency goals. An Advanced Physical Option provides physically aware synthesis capabilities so that logic designers can account for the physical interconnect, without having to learn how to do physical design.

Encounter RTL Compiler Datasheet »
Encounter RTL Compiler Advanced Physical Option Datasheet »
EE Journal Chalk Talk: Physically Aware Synthesis Techniques »

Encounter RTL Compiler/Advanced Physical Option With its combination of breakthrough algorithms, efficient data structures, and modern programming techniques, Encounter RTL Compiler delivers strong speed, area, and power advantages for the most challenging designs. New advanced, production-proven, global synthesis technology further improves these results while delivering even faster runtimes. At the core of Encounter RTL Compiler is a breakthrough synthesis algorithm—global mapping. This technique devotes more time to examining the overall solution space to deliver an optimized netlist for meeting your design intent goals throughout physical design.

Encounter RTL Compiler performs multi-objective optimization that simultaneously considers timing, power, and area intent to create logic structures that converge on all these goals in a single pass. The Advanced Physical Option provides high-capacity physical synthesis that, combined with the production placement engine in Encounter Digital Implementation System, helps logic design teams easily predict, visualize, and fix physical issues that affect closure on a project’s power, performance, and area (PPA) intent. This option results in faster physical design closure by improving predictability and convergence on silicon quality goals through a robust suite of physical synthesis features.

  • A well-balanced logic structure isolates critical paths, reduces power, area, and congestion in off-critical logic, and enables faster timing closure and design convergence through placement and routing
  • Physical layout estimation (PLE) technology eliminates the need for wireload models by modeling physical interconnect at a higher level of abstraction for use in RTL-to-gate optimization
  • Encounter RTL Compiler Advanced Physical Option incorporates Encounter Digital Implementation System placement technology into synthesis, providing real physical timing to logic structuring, mapping, optimization, and analysis. This option improves predictability of physical design closure, increases overall quality of silicon, and reduces schedule risk.
  • Encounter RTL Compiler Low Power Option reduces power consumption through single-pass multi-Vt optimization, hierarchical and multi-stage clock gating, true top-down multi-supply voltage exploration and synthesis, and full power shutoff support with Common Power Format (CPF) and IEEE 1801
  • Multi-bit cell inferencing allows for the merging of single registers into mutli-bit registers (when available in a target library) to share clock enables and low overall chip power
  • Shrinks die sizes with multi-objective optimization, which creates smaller logic structures for non-timing-critical regions
  • Multi-mode synthesis optimization and analysis accelerates overall turnaround time to design closure for complex chips with multiple functional modes
  • Is easy to adopt—uses standard inputs and outputs so that, if you require improved quality of silicon (timing, area, and power after wires), you can quickly achieve your design goals