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Logic Design 

Chip planning
Decisions made during the architectural phase of the IC design cycle have a major impact on the ultimate size, power consumption, performance, and cost of the final chip. Cadence® chip planning solutions enable design teams to balance these often conflicting goals by performing rapid what-if analysis and optimizing design specifications to achieve an optimal chip plan.

Cadence InCyte Chip Estimator
Enables accurate estimation of IC size, power consumption, leakage, performance achievability, and cost.  Provides an architectural exploration environment where users can quantify and compare a vast number of chip implementation options to balance technical and economic goals.
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Cadence Chip Planning System
An enterprise-class IC planning and IP reuse environment designed for larger, global organizations needing the utmost in technical and economic estimation accuracy.  Provides support for estimation with custom IP and manufacturing processes. Features a comprehensive IP reuse management system.
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