F5 Networks Inc
Martin Spohr, Senior Engineer, NEC Electronics from NEC Video talks about using Encounter Conformal Constraint Designer to overcome nanometer design challenges.
Bruce Cory, DFT Methodology Manager from nVidia talks about the importance of test coverage and how Cadence Encounter Test delivered quality in several situations.
Chris Malachowsky, VP of Engineering from NVIDIA talks about the challenges of dealing with 90 and 65 nanometer technologies, and how Cadence technologies and partnering approach help NVIDIA get results.
Amit Chandra, Sr. Engineering Manager of P.A. Semi talks about using the Encounter platform to overcome high-performance, low power design challenges.
Dan Dobberpuhl, President and CEO of P.A. Semi talks about using the Encounter platform to overcome high-performance, 65nm design design challenges.
TSMC North America
David Lan, Senior Manager, Design Methodology from TSMC North America collaborates with Cadence to offer 90-nanometer design solutions to its customers.
Thilo von Selchow
Thilo von Selchow, CEO from ZMD talks about how ZMD and Cadence Engineering Services work together to produce cutting-edge ZigBee wireless solutions.
In this video from CDNLive EMEA 2014, Steven Holloway, Principal Verification Engineer of Dialog Semiconductor, discusses how he needed to successfully verify the register map in his parametric projects, while working around complex access policies, rapidly changing specifications, and the need to complete verification in an overnight regression run. Using Cadence's RegVal formal app flow, Holloway was able to automatically generate properties based on specifications, allowing him to run a validation regression on all 900 registers on the chip in six hours of CPU time and quickly debug any problems, all with less set-up time than it would take to put together a test bench.
Anis Jarrar, Principal Design Engineer, at Freescale Semiconductor describes how they utilized the Cadence Low-Power Solution to design and implement the complex Kinetis SoC.
Designing a networking chip with a hierarchical design can be very challenging in terms of timing correlation between synthesis and implementation and congestion after scan insert. Raghavendra Prasad, a senior design engineer at MegaChips, talks about how much measurable improvement the company gained by applying physically aware synthesis with Cadence® Encounter® RTL Compiler with Physical. Watch the video to learn how to avoid surprises in layout.
Samuele Raffaelli, a digital designer at STMicroelectronics, talks about how he and his team used, as a first step in verification, a formal verification methodology based on Cadence's Incisive® Formal Verifier and Incisive Enterprise Verifier for "exhaustive verification of the RTL." Watch the video to learn how the team reduced its verification time from 12 to 8 weeks.