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Incisive Formal Verifier 


Assertion-based verification and debug of RTL block designs

Incisive Formal Verifier brings formal analysis to the designer’s desktop. By detecting errors prior to testbench availability, it enables verification very early in the design cycle and shortens the time to design convergence.

Incisive Formal Verifier Datasheet »
Product ImageCadence® Incisive® Formal Verifier allows design teams to start RTL block verification months earlier than when using traditional simulation-based techniques. Its formal, assertion-based approach and exhaustive analysis capabilities ensure verification quality by pinpointing the source of bugs and detecting the corner-case errors that other methods often miss. Incisive Formal Verifier integrates easily into established design and assertion-based verification flows through its support of industry-standard languages. Of course, Incisive Formal Verifier is optimized to contribute data and coverage metrics to further accelerate a metric-driven SoC and Silicon Realization flow.

Additionally, new applications like SoC Connectivity checking and Assertion-Based Verification IP provide mathematically exhaustive automation of verification processes that can break simulation-only approaches. Learn more about all the ‘verification apps’ approach and offerings here

Features/Benefits
  • Speeds time to block design closure with early error detection, analysis, and debug
  • Reduces risk of re-spin by finding bugs that other verification approaches miss
  • Eases chip-level verification by delivering higher block-level verification quality
  • Leverages the same assertions as Incisive simulation, acceleration, and emulation technologies for SoC and Silicon Realization
  • Supports all industry-standard assertion formats, including SystemVerilog Assertions (SVA), Property Specification Language (PSL), the Open Verification Library (OVL), and the Incisive Assertion Library