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Encounter Timing System  


Unified timing analysis for faster design closure and signoff

Encounter® Timing System tightly couples the design implementation environment with the timing signoff environment. This improves timing convergence throughout the design flow and greatly reduces the time to design closure. As a complete standalone solution, Encounter Timing System offers silicon-accurate timing signoff and signal integrity analysis that ensures operational chips after tapeout.

Encounter Timing System Datasheet »

Product Image Encounter Timing System is a full-chip static timing analysis (STA) solution providing gate-level delay calculation, signoff-level timing and signal integrity (SI) analysis, statistical timing and leakage analysis, advanced on-chip variation analysis, and advanced node functionality required for double-patterning and waveform effects.

Encounter Timing System removes the iteration bottleneck by providing a consistent, integrated Common Timing Engine for both the design implementation stage and the final timing verification stage of the design cycle. The result is correlation and convergence between implementation and signoff for faster timing closure.

Benefits
  • Advanced timing solution with comprehensive analysis
    • Delay calculation
    • Static timing analysis
    • SI analysis
    • Statistical timing analysis
    • On-chip variation analysis
  • Integrated with EDI System
    • Consistent timing analysis during implementation throughout the flow and signoff at the end of the flow
    • Faster design convergence and timing closure with smaller design margin
    • Common database infrastructure for fast setup and a consistent usage model throughout the flow
  • Unmatched timing signoff accuracy
    • Prevents excessive over-design to exceed performance, power, and area targets
    • Delivers accurate base delay and SI delay calculation to within 2-5% of SPICE
    • Leverages current source models for greater accuracy on mainstream and advanced node designs
    • Offers built-in critical path simulation for delay and SI correlation with SPICE
  • Higher throughput for shorter design cycles and faster time to design signoff
    • End-to-end multi-threaded timing and SI analysis for faster signoff turnaround
    • Concurrent multi-mode/multi-corner (MMMC) timing and SI analysis for large view-count designs
    • Distributed multi-CPU and multithreaded processing for maximum hardware utilization
  • Higher productivity to shorten tapeout schedules by weeks
    • Industry-renowned global timing debug to accelerate root-cause and bottleneck analysis
    • MMMC-aware timing debug for quick timing issue identification across all views
    • MMMC signoff ECO optimization and repair across all timing views for fewer ECO cycles
  • Supported by major foundries, ASIC, and IP vendors, and used exclusively by multiple IDMs for signoff