Fast and accurate bug detection and correction, from RTL to layoutVerify and debug multimillion-gate designs—early in the design cycle—without using test vectors. Encounter Conformal Equivalence Checker drives design convergence by reducing the risk of missing critical bugs in complex datapaths, digital custom logic, custom memories, and FPGAs. Encounter Conformal Equivalence Checker Datasheet » |
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Already proven in thousands of tapeouts, Encounter® Conformal® Equivalence Checker is the industry’s most widely supported equivalence checker. Faster than conventional gate-level simulation, it verifies the broadest variety of circuits including complex arithmetic logic, custom memories, and custom digital logic.
Features/Benefits
- Uses abstraction techniques to exhaustively verify multimillion-gate ASICs and FPGAs several times faster than traditional gate-level simulation
- Decreases the risk of missing critical bugs with independent verification technology
- Enables faster, more accurate bug detection and correction throughout the entire design flow, driving convergence on design and verification goals
- Pinpoints the location of failing points in a design and offers a rich set of diagnosis tools to help users resolve issues
- Extends equivalence checking capability to complex datapaths, enables the use of multi-threads to speed up verification runs, and closes the RTL-to-layout verification gap (XL configuration)
- Ensures RTL models perform the same functions as the corresponding transistor circuits implemented on silicon through the use of advanced transistor abstraction techniques and equivalence checking (GXL configuration)
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