Fast and accurate bug detection and correction, from RTL to layoutEncounter Conformal Equivalence Checker helps designers verify and debug multimillion-gate designs—early in the design cycle—without using test vectors. It can handle complex datapaths, digital custom logic, custom memories, and FPGA designs, decreasing the risk of missing critical bugs. Encounter Conformal Equivalence Checker Datasheet » |
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Already proven in thousands of tapeouts, Cadence® Encounter® Conformal® Equivalence Checker is the most widely supported equivalence checker in the industry. It verifies the broadest variety of circuits, including complex arithmetic logic, datapaths, memories, and custom logic, faster than conventional gate-level simulation. It also performs functional checks to verify clock synchronization.
Features/Benefits
- Exhaustively verifies multimillion-gate ASICs and FPGAs several times faster than traditional gate-level simulation
- Decreases the risk of missing critical bugs with independent verification technology
- Enables faster, more accurate bug detection and correction throughout the entire design flow
- Eliminates functional clock domain crossing problems early in the design cycle
- Extends equivalence checking capability to complex datapaths, and closes the RTL-to-layout verification gap (XL configuration)
- Ensures RTL models perform the same functions as the corresponding transistor circuits implemented on silicon (GXL configuration)
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