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Incisive Design Team Manager 

Automated verification management with assertion and test list plans

Incisive Design Team Manager automates and guides verification, from specification to closure. It captures and quickly prioritizes simulation failures, increasing productivity and predictability.

Incisive Design Team Manager Datasheet »
23 resources found
 
Title Type Rated
Power-Aware Verification Spans IC Design Cycle White Paper
Format: .PDF    Date: 12 Dec 2011
 		White Paper
 18
Recommend!
Practical Guide to Low-Power Design - User Experience with CPF
Date: 16 May 2008
 		eBook
 37
Recommend!
Interview: Verification Planning and Management Methodology Focuses on All the Right Things
Format: .PDF    Date: 24 Mar 2008
 		Cadence Article
 6
Recommend!
Interview: By Popular Demand—SystemVerilog Open Verification Methodology
Format: .PDF    Date: 10 Jan 2008
 		Release Information
 3
Recommend!
Integrating Design IP and Verification IP to Ensure Quality and Predictability
Format: .PDF (1.3MB)    Date: 17 Oct 2007
 		Conference Paper
 0
Recommend!
Implementing an Automated Checking Scheme for a Video-Processing Device
Format: .PDF    Date: 15 Sep 2007
 		Conference Paper
 0
Recommend!
Building a SystemVerilog Universal Verification Component with the Incisive Plan-to-Closure Methodology
Format: .PDF (1.5MB)    Date: 15 Sep 2007
 		Conference Paper
 0
Recommend!
Coverage-Driven Verification for Mixed-Signal Systems
Format: .PDF    Date: 15 Sep 2007
 		Conference Paper
 0
Recommend!
Developing a Gigabit Ethernet VIP Using the Plan to Closure Methodology Featuring SystemVerilogpdf
Format: .PDF    Date: 30 Jul 2007
 		Technical Paper
 2
Recommend!
Methods to Improve Verification Quality on the Module Level
Format: .PDF    Date: 15 Jun 2007
 		Conference Paper
 0
Recommend!
Speed up and prove verification by using a generic scoreboard library
Format: .PDF    Date: 15 Apr 2007
 		Conference Paper
 0
Recommend!
Methods to Improve Verification Quality on the Module Level
Format: .PDF    Date: 15 Apr 2007
 		Conference Paper
 0
Recommend!
Test Sequence Reuse from Block to System with the Incisive Plan-to-Closure Methodology
Format: .PDF    Date: 15 Apr 2007
 		Conference Paper
 0
Recommend!
Cadence Low-Power Solution Demo
Date: 29 Jan 2007
 		Demo
 6
Recommend!
Building Transaction-Based Acceleration Regression Environment using Plan-Driven Verification Approach
Format: .PDF    Date: 12 Jan 2007
 		Conference Paper
 0
Recommend!
Working with Interfaces, EZ-start Guide
Format: .PDF    Date: 27 Oct 2006
 		Application Brief
 0
Recommend!
Packaging Reusable Components, EZ-start Guide
Format: .PDF    Date: 02 Oct 2006
 		Application Brief
 0
Recommend!
Beyond the Compliance Checklist
Format: .PDF    Date: 18 Aug 2006
 		Cadence Article
 0
Recommend!
Do's and Dont's for Systematically Implementing Late Engineering Changes on Your Project
Format: .PDF    Date: 10 Jun 2006
 		Cadence Article
 0
Recommend!
Leveraging Assertions in System Verilog Testbench to get to Closure
Format: .PDF    Date: 23 Mar 2006
 		Conference Paper
 0
Recommend!
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