Take the risk out of full-chip low-power verificationEncounter Conformal Low Power combines equivalence checking and functional checks, using formal techniques to enable full-chip verification of designs optimized for low power. Encounter Conformal Low Power Datasheet » |
|
|
|
|
 Optimizing designs for leakage and dynamic power helps designers reduce energy consumption and packaging costs. But these advanced low-power design methods also complicate the verification task, introducing risk during synthesis and physical implementation. Full-chip, gate-level simulation is not a practical or scalable methodology for verifying today’s large, complex designs. Cadence® Encounter® Conformal® Low Power enables designers to verify and debug multimillion-gate designs optimized for low power, without simulating test vectors. It combines low-power structural and functional checks with world-class equivalence checking to provide superior performance, capacity, and ease of use. Features/Benefits
- Minimizes silicon re-spin risk by providing complete verification coverage
- Detects low-power implementation errors early in the design cycle
- Verifies multimillion-gate designs much faster than traditional gate-level simulation
- Closes the RTL-to-layout verification gap
- Decreases risk of missing critical bugs through independent verification technology
|
|
|
|
|