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Home > Tools > Logic Design > Encounter Conformal Low Power

Encounter Conformal Low Power 

Fast and accurate creation, verification, and integration of power intent

Encounter Conformal Low Power enables the creation and validation of power intent in context of the design. Combines low-power equivalence checking with structural and functional checks to enable full-chip verification of power-efficient designs.

Encounter Conformal Low Power Datasheet »

Product ImageOptimizing designs for leakage and dynamic power helps designers reduce energy consumption and packaging costs. But these advanced low-power design methods also complicate the verification task, introducing risk during synthesis and physical implementation. Full-chip, gate-level simulation is not a practical or scalable methodology for verifying today’s large, complex designs. Encounter® Conformal® Low Power enables designers to create power intent, then verify and debug multimillion-gate designs optimized for low power, without simulating test vectors. It combines low-power structural and functional checks with world-class equivalence checking to provide superior performance, capacity, and ease of use.

  • Reduces the risk of silicon re-spins by providing complete verification coverage
  • Detects low-power implementation errors early in the design cycle
  • Verifies multimillion-gate designs much faster than traditional gate-level simulation
  • Closes the RTL-to-layout verification gap using low-power equivalence checking
  • Decreases the risk of missing critical bugs through independent verification technology
  • Enables power intent creation and integration, without having to become a power format expert